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Workshop on Computer Architecture Research with RISC-V (CARRV)
March 5, 2021 @ 8:00 am - 5:00 pm PST
Fifth Workshop on Computer Architecture Research with RISC-V (CARRV 2021)
in conjunction with ISCA’21
Virtual Workshop
June 17, 2019
IMPORTANT DATES:
Abstract submission deadline: May 7, 2021
Full paper submission deadline: May 14, 2021, 23:59 PST
Author notification: May 21, 2021
The Fifth Workshop on RISC-V for Computer Architecture Research (CARRV) seeks original research papers on the design, implementation, verification, and evaluation of RISC-V cores, SoCs, and accelerators. Submission of early work across simulated, FPGA and hardware implementations is encouraged.
The topics of specific interest for the workshop include, but are not limited to:
– RISC-V cores and SoC architectures
– RISC-V ISA extensions
– RISC-V-based hardware accelerators
– Security architectures and techniques
– Formal methods
– Verification methodologies
– Hardware/software interfaces
– RISC-V ISA and implementation performance analysis
– RISC-V compilers and dynamic translation tools
Submission instructions are available at the workshop web site.