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X-WR-CALDESC:Events for RISC-V International
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SUMMARY:RISC-V at Microelectronics UK
DESCRIPTION:Come see us\, SiFive and MIPS by GF at the RISC-V hub located in the front of Microelectronics UK! \nSept 29 – 30 in Excel London \nDay 1 @ 12:45pm – RISC-V\, SiFive & MIPS by GF will be on a Panel – “RISC-V and the Future of Open Architectures“ \nComputing is evolving rapidly\, with new requirements for AI\, safety\, security\, power efficiency and connectivity to meet the demands of future applications. To achieve your design goals\, customization is key. RISC-V is the open standard Instruction Set Architecture (ISA) that a whole ecosystem of companies is basing their products on\, from chips\, to silicon IP\, to EDA tools\, and software solutions. They are using the inherent customizability and extendibility of the RISC-V standard to deliver differentiated products that tackle specific market needs in a targeted way that has not been possible until now. \nCome to this session to hear how RISC-V addresses markets across the compute spectrum\, from IoT to Automotive to Industrial and beyond\, and how computing based on the RISC-V open standard can enable you to deliver a more optimized\, innovative product roadmap to market faster than ever before.
URL:https://riscv.org/event/risc-v-at-microelectronics-uk/
LOCATION:Excel London\, Royal Victoria Dock\, 1 Western Gateway\, London\, United Kingdom
ATTACH;FMTTYPE=image/png:https://riscv.org/wp-content/uploads/2026/09/Microelectronics-UK-logo.png
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