RISC-V Foundation Events


RISC-V: Delivering Open and Secure Solutions

May 21, 2019 from 5:30 – 8:00 p.m. PT

David’s Restaurant

Santa Clara, Calif.

Hosted by SecureRF, Imperas Software and Andes Technology

Registration: To RSVP, please visit here.


Second Cambridge RISC-V Meetup

June 19, 2019 from 6:30 – 8:00 p.m. GMT

Westminster College Cambridge

Cambridge, U.K.

Hosted by UltraSoC and Imperas Software

Registration: To RSVP, please visit here.


RISC-V Workshop Zurich

June 11-13, 2019

ETH Zurich

Zurich, Switzerland

Registration: To register, please visit here.


RISC-V Summit

Dec. 9-12, 2019

San Jose, Calif.

Stay tuned for details on the call for speakers and registration.



If you’re interested in sponsoring or exhibiting at any RISC-V Foundation events, please visit here or contact Lori at lori.mikuls@informa.com.


Industry Events


Technical Symposium RISC-V Moscow

May 20, 2019

Moscow Holiday Inn Lesnaya Hotel

Moscow, Russia

The RISC-V Moscow Technical Symposium is supported by SiFive , founded by the inventors of the RISC-V architecture, and Syntacore , the leading developer of the RISC-V compatible IP processor.

The event will feature presentations by leading industry experts, as well as RISC-V ecosystem companies and universities. Participants will learn about the RISC-V ISA, recent ecosystem developments, standard and specialized RISC-V cores and platforms offered by ecosystem companies, and SaaS, an approach that facilitates access to developments. Companies will also demonstrate commercially available RISC-V cores, boards and tools for developers, platforms based on RISC-V SoC, as well as finished products based on RISC-V IP.

Registration: To register, please visit here. Participation for specialists is free.


Technical Seminar in Korea on Methodology for Designing a RISC-V SoC

May 30, 2019

Stanford(13449) 232, LH Business Growth Center, 54, Changeop-ro, Sujeong-gu,

Gyeonggi-do, Republic of Korea

Co-hosted by Imperas, Andes and UltraSoC on the Methodology for Designing a RISC-V SoC. This seminar will provide engineers with an overview of the steps needed to build a RISC-V based SoC, including processor design (custom instructions) and verification, processor and SoC debug, and software porting and bring up. Examples of use cases will also be presented. Featured presenters will include Andes, Coontec, ETRI, Imperas, UltraSoC and other invited guests, plus demonstration and networking session to follow.

Registration: To register, please visit here.


Design Automation Conference

June 2-6, 2019

Las Vegas, NV

The Design Automation Conference (DAC) is recognized as the premier conference for design and automation of electronic systems. Some of the member exhibiting include: SiFive, Google, Samsung, Andes, Cadence, Huawei, IBM, Imperas, Mentor, OneSpin, SureCore, TSMC, UltraSoC, MOSIS

Registration is now closed.


CHIPS Alliance Workshop

June 19, 2019

Sunnyvale, CA

Hosted by The Linux Foundation

CHIPS Alliance will be holding their inaugural workshop on June 19th. The workshop will focus on open source hardware, software tools, RTL development and related topics. Presentations will be made by member companies and attendees will also have a forum to propose RTL design and development ideas. Workshop attendees will learn more about our organization and the RTL designs we will be developing. Attendees can network and meet with CHIPS Alliance members and the board of directors.

Registration: To register, please visit here.


CARRV 2019: Third Workshop on Computer Architecture Research with RISC-V

June 22, 2019

Phoenix, Ariz.

The event is co-located with ISCA 2019. The call for papers deadline is March 29, 2019. Please submit here.


Hot Chips: A Symposium on High Performance Chips

Aug. 18-20, 2019


Palo Alto, Calif.

Since it started in 1989, HOT CHIPS has been known as one of the semiconductor industry’s leading conferences on high-performance microprocessors and related integrated circuits. The conference is held once a year in August in the center of the world’s capital of electronics activity, Silicon Valley.

The conference emphasis this year, as in previous years, is on real products and realizable technology. Submissions are invited from a variety of “hot” topics, including embedded and reconfigurable processors, quantum computing, nano structures, wireless chips, network/security processors, advanced packaging technology etc. For a complete list of topics, refer to the official call for papers.

To check out the call for paper and poster submission, please visit here. Stay tuned for details on registration.