RISC-V Training Partners are focusing on RISC-V training in a professional setting. RISC-V International provides this Training Partner Program in order to extend the breadth and reach of RISC-V knowledge (disruptive technology), provide opportunities for a broader audience to teach and learn, and engage the community to achieve expertise in the critical areas needed for a healthy ecosystem while we share the message and benefits of open collaboration.
Edacentrum / Scale4Edge
The edacentrum is the network for electronics, design and applications in business and science. As an independent authority, the edacentrum designs research & development for a consistent design methodology along the entire value chain. In this role, the edacentrum is a recognized innovation accelerator for the microelectronics industry and its user industries.
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Edaptive Computing, Inc (ECI)
Edaptive Computing, Inc (ECI) is a RISC V International training partner. ECI provides training in formally verifying RISC-V (pipeline architecture of RISC-V ISA, architecture register modeling and specifications to verify interrupts, exceptions and flushes) using OneSpin tools and verification of security properties (maintaining security in a design’s control and status registers, validating the functionality of physical memory protections, and identifying side-channel vulnerabilities) using Tortuga Logic tools, combined with emulation and simulation.
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ISCAS – PLCT Lab
The PLCT lab is providing developing skills for RISC-V related compilers, emulators and language virtual machines. Through the training program you could learn the skills needed for writing new LLVM backends for RISC-V CPUs, and the skills for extending QEMU/Spike to support new RISC-V SoC.
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Maven Silicon – Centre of Excellence in VLSI
Maven Silicon is one of RISC-V’s global training partners. As a center of excellence in VLSI, Maven Silicon collaborates with multinational semiconductor corporations and academia to upskill their engineers worldwide, offering various online, offline and blended VLSI courses. Our courses’ portfolio includes SoC & IP – RTL design and verification, Languages & Methodologies – Verilog, SystemVerilog, UVM, and DFT, STA, Low Power DV, CDC, Physical Design & Verification.
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MINRES helps customers to establish and improve embedded software engineering processes, methodologies and techniques tailored to meet their specific requirements and capable to adapt to future needs. We provide training for customers who want to get started with RISC-V based projects. We work together with Eclipseina and the Embedded Academy to organize these training sessions. See our training page for more details.
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For 25 years PLC2 have been at the forefront of embedded system training in Europe, focusing upon not only FPGA training but also HDL languages, embedded system, operating system, and system level design challenges.
To achieve the demands placed upon modern embedded system developments, they utilize not only programmable logic but also embedded processors. Increasing in popularity are soft core RISC-V processor implementations which provide an open source solution and technology independent solution.PLC2 is pleased to announce it will be introducing several RISC-V training courses which will focus upon not only the implementation of the RISC-V processor within FPGA fabric. But will address the entire eco system from RISC-V ISA & ISA Compliance, Implementing RISC-V solutions in programmable logic to working with operating systems and Cyber Security.
View PLC2’s Training Offering