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Senior Hardware Engineer

Senior Hardware Engineer

Website Codasip

Cutting-edge processor IP based on the RISC-V open ISA

Codasip was founded on a simple belief – that we could bring together the brilliance of microprocessor architects and software engineers and capture it in tools that made design simpler, faster, and less expensive. STUDIO was born in 2014 with the mission of democratizing processor design. We are succeeding. At the same time, RISC-V was gaining traction, so it was natural for Codasip to embrace it as an Open Instruction Set Architecture (ISA).

Codasip is expanding in the UK. We are looking for Hardware Engineers at all levels to build out our team and help deliver and expand our product roadmap. The role can be based in either our Bristol or Cambridge offices or remotely within the United Kingdom. Besides, you will act in daily concert with our Director of the UK DCs – Simon Bewick

This is an exciting opportunity to join a fast-growing company with a unique position in the industry. If you are proactive, you are not afraid to voice your own opinion and are looking for a job where you can be creative, we think you will work well with us.


Microarchitecture definition and implementation of RISC-V processors and extensions
Processor development in our architecture language (CodAL)
Working closely with the verification team on verification planning, debugging and final sign-off
Technical specification and documentation writing
Synthesis (timing and area optimizations) to ensure PPA targets can be met
Be responsible for defining, estimating and tracking your own work


Over 5 years recent and relevant design experience with at least one HDL (VHDL/Verilog/SystemVerilog)
Knowledge of computer systems and architecture
Ability to write clear and concise code
Experience with digital circuit simulation
User knowledge of Linux
Knowledge of versioning tools (Git, SVN)
Knowledge of scripting languages (Shell, Bash, Python)
Analytical thinking, self-sufficiency, team collaboration
Ability to work across teams to debug issues and find root causes


Knowledge of RISC-V instruction set
Advanced knowledge of computer systems and architecture
Experience with Synthesis, Design for Test and Timing Analysis
Knowledge of C/C++


Good degree (BSc, MSc, BEng, MEng or equivalents) in a numerate discipline

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