As the leader of a CPU software engineering team, the candidate will collaborate across MIPS business and technical teams to turn business requirements into software products to support MIPSCPU IP. The candidate will build and lead the implementation team to create software products for use In-vehicle Infotainment (IVI), 5G Communications, Data Center applications involving video processing, data streaming and Edge AI and ML applications. The role involves collaborating with business and technical teams as well as interfacing with customers and RISC-V international.

You will:
Recruit and build high performance software engineering team
Engage with CPU technical teams including architecture, design, verification, and platforms, as well as business teams to collaborate in product definition of features.
Engage with customers where required to understand detailed technical requirements.
Create implementation plans including specifications, product documentation, coding, and software validation.
Create software product including low level CPU software, Linux kernel features, toolchains, and simulators.
Ownership of complex CPU software products from definition to production

Ideally, you will have:
Bachelor of Science degree in EE/ECE/CE/CS or related field required; MS or PhD highly desired
10+ years experience in complex CPU implementations
Strong coding (C, C++) and scripting (csh, bsh, Python/Perl) experience
Understanding and experience with performance simulators
Software development best practices, including test-driven design, continuous integration
Knowledge of microprocessor architecture and micro-architecturesuch as:
Instruction fetch and decode, branch prediction
Instruction scheduling and register renaming
Out-of-order execution
Integer and floating-point execution
Load/store execution, prefetching
Cache and memory subsystems
Virtual memory management

Areas Of Expertise (the More The Better):
Candidates should have expertise in multiple of the following areas:
Experience with RISC-V, ARM, and/or MIPS CPU
Experience with CPU features such as multi-threading, virtualization, multi-core, multi-cluster, and vector designs
Experience with toolchain development
Experience with Linux kernel development
Experience with performance simulators
Experience with AI/ML

Here’s what you can expect from us:
At MIPS, you’ll be a member of a fast-growing team of technologists that are creating the industry’s highest performance RISC-V processors.  Small teams that are part of a non-compartmentalized structure – you’ll be able to understand and have an impact on the bigger picture. A great deal of autonomy, with support from some of the industry’s most experienced CPU engineers. An unlimited growth path – with the right skills, you can decide where you want to expand and grow in your role at MIPS. The opportunity to learn a great deal about the blossoming RISC-V architecture in cutting edge applications with industry leading customers.

At MIPS we provide meaningful benefits programs and products to our associates and their families. MIPS offers a competitive benefits package that includes medical, dental, vision, retirement savings, and paid leave!

More about us:
MIPS is well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original MIPS RISC architecture, MIPS processors have shipped into billions of consumer and enterprise products.

Today, MIPS is once again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products: the MIPS eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, MIPS can accelerate development and deployment of RISC-V based solutions.