RISC-V International Board of Directors


Krste Asanovic – Chairman of the Board

Krste Asanović is a professor in the EECS Department at the University of California, Berkeley (UC Berkeley). He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005, before returning to join the faculty at UC Berkeley in 2007. His main research areas are computer architecture, VLSI design, parallel programming and operating system design. He is currently director of the UC Berkeley ASPIRE lab tackling the challenge of improving computational efficiency now that transistor scaling is ending. He leads the free RISC-­V ISA project at UC Berkeley, serves as chairman of RISC-V International, and co­founded SiFive Inc. to support commercial use of RISC­-V processors. He received the NSF CAREER award, and is an ACM Distinguished Scientist and an IEEE Fellow.



Zvonimir Bandic

Zvonimir Z. Bandić is a research staff member and senior director of Next Generation Platform Technologies at Western Digital Corporation in San Jose, Calif. He received his Bachelor of Science in electrical engineering in 1994 from the University of Belgrade, Yugoslavia, and his Master of Science (1995) and PhD (1999) in applied physics from Caltech, Pasadena, in the field of novel electronic devices based on wide bandgap semiconductors. He is currently focusing on both NAND and emerging Non-Volatile Memories (PCM, ReRAM, MRAM) applications for data center storage and computing, including CPU, memory, networking and storage. He has been awarded over 50 patents in the fields of solid state electronics, solid state disk controller technology, security architecture and storage systems and has published over 50 peer-reviewed papers.



Charlie Hauck

Charlie is CEO of Bluespec, Inc., a provider of high­-level tools and IP for ASIC and FPGA design. Before Bluespec, he was general manager of Faraday Technology USA, a fabless ASIC company. Charlie has over 25 years of experience in marketing and developing RISC processors at Lexra, LSI Logic, Kendall Square Research and Commodore. Charlie received a Bachelor of Science from Johns Hopkins University and a Master of Science from the Massachusetts Institute of Technology.


Rob Oshana

Rob Oshana is vice president of software engineering R&D for NXP Microcontrollers, where he leads RISC-V efforts across the company.  He is also a member of the RISC-V International board of directors and Chairman of the Board for the OpenHW Group.  He is a recognized international speaker and a senior member of IEEE.  He is also an adjunct professor at Southern Methodist University and the University of Texas.


Dave Patterson

David Patterson – Vice Chair

David Patterson is likely best-known for the book Computer Architecture: A Quantitative Approach written with John Hennessy for Berkeley research projects Reduced Instruction Set Computers (RISC), Redundant Arrays of Inexpensive Disks (RAID), and Network of Workstations. He also served as UC Berkeley’s Computer Science Division chair, the Computing Research Association chair, and president of the Association for Computing Machinery. Additionally, David was elected to the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame. He received the Berkeley Citation in 2016, which is given to distinguished individuals who go beyond the call of duty and whose achievements exceed the standards of excellence in their fields.


Frans Sijstermans

Frans Sijstermans is a vice president of engineering at NVIDIA. He is responsible for the architecture and implementation of multi media hardware components, including camera interface, video codecs, image processing and computer vision accelerators, and display controllers. Besides multimedia, his interests include processor architectures, deep learning, and security. He holds a Master of Science degree from Eindhoven University of Technology in the Netherlands.


Ted Speers

Ted Speers

Ted Speers is head of product architecture and planning for Microchip’s FPGA BU, where he is responsible for defining its roadmap for low power, secure, reliable FPGAs and SoC FPGAs. He joined Actel (now part of Microchip) in 1987 and held roles in process engineering and product engineering before assuming his current role in 2003. He is a Technical Fellow and co-inventor on 35 U.S. patents. Prior to joining Actel, he worked at LSI Logic. Ted has a Bachelor of Science in chemical engineering from Cornell.


RISC-V International Executives

Calista Redmond – CEO

Calista Redmond is the CEO of RISC-V International with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond RISC-V International. Prior to RISC-V International, Calista held a variety of roles at IBM, including Vice President of IBM Z Ecosystem where she led strategic relationships across software vendors, system integrators, business partners, developer communities, and broader engagement across the industry. Focus areas included execution of commercialization strategies, technical and business support for partners, and matchmaker to opportunities across the IBM Z and LinuxOne community. Calista’s background includes building and leading strategic business models within IBM’s Systems Group through open source initiatives including OpenPOWER, OpenDaylight, and Open Mainframe Project. For OpenPOWER, Calista was a leader in drafting the strategy, cultivating the foundation of partners, and nurturing strategic relationships to grow the org from zero to 300+ members. While at IBM, she also drove numerous acquisition and divestiture missions, and several strategic alliances. Prior to IBM, she was an entrepreneur in four successful start-ups in the IT industry. Calista holds degrees from the University of Michigan and Northwestern University.


Stephano Cetola – Technical Program Manager

Stephano Cetola is the technical program manager for RISC-V International. Stephano’s deep technical background dates back to the late 90’s where he worked building websites using Perl. He has worked on and managed numerous open source initiatives in software and hardware. Stephano was most recently employed at Intel contributing to the Yocto Project building embedded Linux distros and working on TianoCore, an open source implementation of UEFI. Throughout his career Stephano has been a tireless proponent of open source software, firmware, and hardware. He is currently working on his ECE master’s degree at Portland State University focusing on embedded systems and SoC design.

Jeffrey “Jefro” Osier-Mixon – Program Manager

Jeffrey Osier-Mixon is the program manager for RISC-V International and other projects managed by the Linux Foundation. Jefro comes from an open source background starting at Cygnus Support in the early 1990s, and has spent most of his career as a technical writer and developer focused on hardware and embedded systems. He served as the community manager and board chair for the Yocto Project from 2011 to 2018 while working at Intel, where he also helped launch the Zephyr Project and Project ACRN. He has been involved with the Embedded Linux Conference since 2008 and speaks at several open source conferences annually. Jefro holds a Bachelor of Arts from the University of California Santa Cruz.