RISC-V International Board of Directors

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Krste Asanovic – Chairman of the Board

Krste Asanović is a professor in the EECS Department at the University of California, Berkeley (UC Berkeley). He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005, before returning to join the faculty at UC Berkeley in 2007. His main research areas are computer architecture, VLSI design, parallel programming and operating system design. He is currently director of the UC Berkeley ASPIRE lab tackling the challenge of improving computational efficiency now that transistor scaling is ending. He leads the free RISC-­V ISA project at UC Berkeley, serves as chairman of RISC-V International, and co­founded SiFive Inc. to support commercial use of RISC­-V processors. He received the NSF CAREER award, and is an ACM Distinguished Scientist and an IEEE Fellow.

 

Dave Patterson

David Patterson – Vice Chair

David Patterson is likely best-known for the book Computer Architecture: A Quantitative Approach, written with John Hennessy and for the UC Berkeley research projects Reduced Instruction Set Computers (RISC), Redundant Arrays of Inexpensive Disks (RAID), and Network of Workstations (NOW). He also served as UC Berkeley’s Computer Science Division chair, the Computing Research Association chair, and president of the Association for Computing Machinery. Additionally, David was elected to the National Academy of Engineering, the National Academy of Sciences, and shared the 2017 ACM A.M. Turing Award with Hennessy.

 

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Zvonimir Bandic – Treasurer

Zvonimir Z. Bandić is a research staff member and senior director of Next Generation Platform Technologies at Western Digital Corporation in San Jose, Calif. He received his Bachelor of Science in electrical engineering in 1994 from the University of Belgrade, Yugoslavia, and his Master of Science (1995) and PhD (1999) in applied physics from Caltech, Pasadena, in the field of novel electronic devices based on wide bandgap semiconductors. He is currently focusing on both NAND and emerging Non-Volatile Memories (PCM, ReRAM, MRAM) applications for data center storage and computing, including CPU, memory, networking and storage. He has been awarded over 50 patents in the fields of solid state electronics, solid state disk controller technology, security architecture and storage systems and has published over 50 peer-reviewed papers.

 

Yungang Bao

Yungang Bao is a Professor of Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) and the director of Research Center of Advanced Computer Systems (ACS) of ICT-CAS. Prof. Bao founded China RSIC-V Alliance (CRVA) and serves as the secretary-general of CRVA. His research interests include computer architecture and computer systems. His research work such as Labeled von Neumann Architecture (LvNA), Hybrid Memory Trace Tool (HMTT), Partition-Based DMA Cache and PARSEC 3.0 has been adopted by the industry including Alibaba, Huawei, Intel and the research community. He was a plenary keynote speaker at China National Computer Congress (CNCC) in 2016 and was invited to give a keynote presentation at ARM Research Summit 2018. He was the winner of CCF-Intel Young Faculty Award of the year for 2013. He won CCF-IEEE CS Young Computer Scientist Award and China’s National Lofty Honor for Youth under 40 of the year for 2019.

 

Richard Bohn – Seagate Technology

Richard Bohn is a Managing Principal Engineer at Seagate Technology, the global leader in data storage solutions. A 16-year silicon industry veteran, Richard has led Seagate’s RISC-V efforts since 2015. Prior to his current role Richard held a number of technical leadership and design positions. He began his career at IBM in processor design. Passionate about the role of open standards and technology, Richard sits on the OpenTitan Technical Committee and Seagate’s Open Source Program Office core team. Richard received a Bachelor of Science and Master of Science in Electrical and Computer Engineering from Carnegie Mellon University.

 

Ken Dockser – Qualcomm

Ken Dockser is Senior Director at Qualcomm where he heads up the Processor Research Team. He has been designing processors for over 30 years in a variety of architectures including VAX, X86, MIPS, PowerPC, ARM and RISC-V. He has expertise in a variety of areas including computer architecture, microarchitecture, arithmetic, verification, benchmarking, software development and marketing. Ken has been active in several industry organizations including IEEE-754 Standard for Floating-Point Arithmetic, Heterogeneous System Architecture (HSA), and Embedded Microprocessor Benchmark Consortium (EMBC). He holds 39 US patents in the area of microprocessor design. Ken serves on the RISC-V Technical Steering Committee, chairs the BitManip Task Group, and is an active participant in many of the task groups – most notably Vector, Compliance, and Cryptography.

 

Jesús Labarta

Jesús Labarta received a B.S. in Telecommunications Engineering from the Technical University of Catalunya (UPC) in 1981 and his Ph.D. in Telecommunications Engineering also from UPC in 1983. He is full professor of Computer Architecture at UPC since 1990 and was Director of CEPBA-European Center of Parallelism at Barcelona from 1996 to 2005. Since its creation in 2005, he has been the Director of the Computer Sciences Research Department within the Barcelona Supercomputing Center (BSC). During his 35-year academic career, Prof. Labarta has made significant contributions in programming models and performance analysis tools for parallel, multicore and accelerated systems, with the sole objective of helping application programmers to improve their understanding of their applications performance and to improve programming productivity in the transition towards very large-scale systems. Under his supervision, his research team has been developing performance analysis and prediction tools (Paraver and Dimemas) and pioneering research on how to increase the intelligence embedded in these performance tools.

 

Frankwell Lin

Frankwell Lin

Frankwell Lin is the President and co-founder of Andes Technology, which is a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores. Frankwell received BSEE degree of Electrophysics from the National Chiao-Tung University, Taiwan, and MSEE degree of Electrical and Computer Engineering from Portland State University, Oregon, USA. Before Andes Technology, he was the spokesperson and board member of Farady, a leading fabless ASIC and silicon IP provider. He also led ASIC business development as starting, then on-and-off leading ASIC implementation, chip backend service, IP business development, industry relationship development (IR) in Faraday. Under his management, Andes Technology has been recognized as one of leading suppliers of embedded CPU IP in semiconductor industry. Andes also won the reputation of leading technology company with awards such like 2012 EE Times worldwide Silicon 60 Hot Startups to Watch, 2015 the Deloitte Technology Fast 500 Asia Pacific award, etc. In 2015, President Lin received accolade award of Outstanding Technology Management Performance, Taiwan, for his contribution to the high-tech industry. In parallel to contribution in the industry, he also contributes time and effort in social service for technology evolution. He is Chairman of TEIA (Taiwan Embedded Industry Alliance) from 2010 to 2012. TEIA is a non-profit organization to promote embedded system innovation as well as embedded system value chain engineering talent training, including embedded software, hardware, IP, application, international promotion channel, etc.

 

Naveed Sherwani

Dr. Naveed Sherwani brings over 30 years of entrepreneurial, engineering, and management experience to his role as Chairman, President and CEO of SiFive. Naveed also serves as the Chairman of SiFive and SemiFive. Naveed has founded or co-founded nine companies including Open Silicon and Brite Semiconductor. He has led over 300 tapeouts throughout his career. He received his Ph.D from the University of Nebraska-Lincoln and, prior to entering the semiconductor industry, was a professor at Western Michigan University, where his research focused on ASICs, EDA, Combinatorics, graph algorithms and parallel computing. Naveed has authored several books and over 100 articles on various aspects of VLSI Physical Design Automation and ASICs.

 

Frans Sijstermans

Frans Sijstermans is a vice president of engineering at NVIDIA. He is responsible for the architecture and implementation of multi media hardware components, including camera interface, video codecs, image processing and computer vision accelerators, and display controllers. Besides multimedia, his interests include processor architectures, deep learning, and security. He holds a Master of Science degree from Eindhoven University of Technology in the Netherlands.

 

Ted Speers

Ted Speers

Ted Speers is head of product architecture and planning for Microchip’s FPGA BU, where he is responsible for defining its roadmap for low power, secure, reliable FPGAs and SoC FPGAs. He joined Actel (now part of Microchip) in 1987 and held roles in process engineering and product engineering before assuming his current role in 2003. He is a Technical Fellow and co-inventor on 35 U.S. patents. Prior to joining Actel, he worked at LSI Logic. Ted has a Bachelor of Science in chemical engineering from Cornell.

 

Dr. Zhangxi Tan

Dr. Zhangxi Tan

Dr. Zhangxi Tan is a co-director of the RISC-V International Open-source Laboratory (RIOS), leading open-source IP and software development that helps the RISC-V ecosystem world-class. Dr. Tan is an adjunct professor at Tsinghua-Berkeley Shenzhen Institute (TBSI). He received his PhD in computer science from UC Berkeley in 2013. He is specialized in computer architecture and VLSI designs. After graduating from Berkeley, he joined Pure Storage (NYSE: PSTG) as a Founding Engineer serving as a lead designer for Pure’s award winning FlashBlade product, which generates hundreds of million-dollar revenues every year and have many high-profile customers. Dr. Tan holds more than 20 US patents in flash storage systems and hardware accelerators. He also founded several startup companies in Silicon Valley and China in the chip design industry.

 

Stefan Wallentowitz

Stefan is a professor at Munich University of Applied Sciences. He is a long term advocate and active member of the open source silicon community, most prominent in his role as director of the Free and Open Source Silicon Foundation (FOSSi Foundation). He has been active in various RISC-V projects over the last six years. Stefan was involved in the debug task group and has recently become chair of the RISC-V SIG “Academia & Education”.

 

Naxin Zhang

Naxin Zhang

Naxin Zhang is a Managing Director of Huawei International responsible for emerging research and open collaboration. He has led multiple architecture/platform initiatives within the company. Prior to Huawei, he worked at HP, Emulex and SMIC. Naxin received a Bachelor of Science from University of Washington and a Master of Science from Stanford University.

 


RISC-V International Executive Staff

Calista Redmond – CEO

Calista Redmond is the CEO of RISC-V International with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond RISC-V International. Prior to RISC-V International, Calista held a variety of roles at IBM, including Vice President of IBM Z Ecosystem where she led strategic relationships across software vendors, system integrators, business partners, developer communities, and broader engagement across the industry. Focus areas included execution of commercialization strategies, technical and business support for partners, and matchmaker to opportunities across the IBM Z and LinuxOne community. Calista’s background includes building and leading strategic business models within IBM’s Systems Group through open source initiatives including OpenPOWER, OpenDaylight, and Open Mainframe Project. For OpenPOWER, Calista was a leader in drafting the strategy, cultivating the foundation of partners, and nurturing strategic relationships to grow the org from zero to 300+ members. While at IBM, she also drove numerous acquisition and divestiture missions, and several strategic alliances. Prior to IBM, she was an entrepreneur in four successful start-ups in the IT industry. Calista holds degrees from the University of Michigan and Northwestern University.


Mark Himelstein – CTO

Before RISC-V international Mark Himelstein was the President of Heavenstone, Inc. which concentrated on Strategic, Management, and Technology Consulting providing hardware and software product architecture, analysis, mentoring and interim management. Previously, Mark started Graphite Systems, Inc (acquired by EMC) where he was the VP of Engineering and CTO developing large Analytics Appliances using highly integrated FLASH memory. Prior to Graphite, Mark held positions as the CTO of Quantum Corp, Vice President of Solaris development engineering at Sun Microsystems and other technical management roles at Apple, Infoblox, and MIPS.

Mark has a bachelors degree in Computer Science and Math from Wilkes University in Pennsylvania and a masters degree in Computer Science from University of California Davis/Livermore. In addition to publishing numerous technical papers and holding many patents, he is the author of the book “100 Questions to Ask Your Software Organization”.


Kim McMahon – Director of Marketing

Kim McMahon is the Director of Marketing of RISC-V International. She comes to RISC-V with a deep background in marketing for open source and technology. She has spent her career with companies such as SGI, Cray, VMware, and the {code} Team at Dell, where she honed her love for HPC, open source, and cloud native. Working with startups, large companies, and all in-between, she brings her expertise in marketing strategy to spread awareness through content and digital platforms. Kim has a Bachelor of Science in Business Administration and Accounting from the University of Northern Colorado. She lives in Winter Park, Colorado and enjoys hiking, skiing, and outdoor activities with her two labradors Coal and Connor.


Stephano Cetola – Technical Program Manager

Stephano Cetola is the technical program manager for RISC-V International. Stephano’s deep technical background dates back to the late 90’s where he worked building websites using Perl. He has worked on and managed numerous open source initiatives in software and hardware. Stephano was most recently employed at Intel contributing to the Yocto Project building embedded Linux distros and working on TianoCore, an open source implementation of UEFI. Throughout his career Stephano has been a tireless proponent of open source software, firmware, and hardware. He is currently working on his ECE master’s degree at Portland State University focusing on embedded systems and SoC design.


Jeffrey “Jefro” Osier-Mixon – Program Manager

Jeffrey Osier-Mixon is the program manager for RISC-V International and other projects managed by the Linux Foundation. Jefro comes from an open source background starting at Cygnus Support in the early 1990s, and has spent most of his career as a technical writer and developer focused on hardware and embedded systems. He served as the community manager and board chair for the Yocto Project from 2011 to 2018 while working at Intel, where he also helped launch the Zephyr Project and Project ACRN. He has been involved with the Embedded Linux Conference since 2008 and speaks at several open source conferences annually. Jefro holds a Bachelor of Arts from the University of California Santa Cruz.


Megan Lehn – Program Manager

Megan Lehn is the program manager for RISC-V International and works as an Event and Meeting Planner at the Linux Foundation. Megan comes from a diverse hospitality, event marketing and sales background and is excited to join the RISC-V International team.