# RISC-V International
> RISC-V: The Open Standard RISC Instruction Set Architecture

## Posts
- [7 Critical Components of the Car of Tomorrow](https://riscv.org/blog/critical-components-car-tomorrow/): With IAA Mobility and the RISC-V Automotive Conference 2025 just around the corner, I’ve pulled together the top themes from
- [RISC-V Edge Inference for Real-Time Eye-Movement Control on GAPses Smart Glasses](https://riscv.org/blog/risc-v-edge-inference-for-real-time-eye-movement-control-on-gapses-smart-glasses/): Project Snapshot This live demonstration showcases GAPses, an ultra-low-power smart-glasses platform based on an ultra-low power RISC-V multicore processor (GAP9),
- [Behind The Scenes of SHD Group’s 2026 RISC-V Market Forecast](https://riscv.org/blog/shd-forecast-2026/): Having spent much of my career flying the flag for B2B tech, I know that belief in the thing you’re
- [We Created a Single Source for All RISC-V Specifications](https://riscv.org/blog/ratified-specifications-library/): The RISC-V Ratified Specifications Library consolidates all of the available RISC-V specifications into one single, accessible repository.
- [Call for Candidates: Help Us Build a Board That Represents Our Entire Ecosystem](https://riscv.org/blog/2026-elections/): Voting is now open for RISC-V International's Board of Directors. Learn how to nominate, understand board member responsibilities, and discover key election dates.

## Pages
- [RISC-V in Automotive](https://riscv.org/industries/automotive-holding/): RISC-V in Automotive Own your silicon roadmap with RISC-V: the industry open standard for the software-defined vehicle. The Software-Defined Vehicle
- [Workload-Specific Silicon | RISC-V in Automotive](https://riscv.org/industries/automotive/workload-specific-silicon/): RISC-V in Automotive→Workload-Specific Silicon As an industry open standard, the RISC-V ISA enables a unified hardware and software ecosystem in
- [RISC-V & Data Centers](https://riscv.org/industries/data-center/): As data center and cloud based services play an increasingly central role across all aspects of society, the infrastructure that
- [Industries](https://riscv.org/industries/)
- [Home](https://riscv.org/): Events RISC-V Summit Europe 2026 Session Videos Are Now Available Catch up on the presentations you missed or revisit your

## Jobs
- [Implementation of the RISC-V ISA Extensions for Control-Flow Integrity (RISC-V Mentorship)](https://riscv.org/job/implementation-of-the-risc-v-isa-extensions-for-control-flow-integrity-risc-v-mentorship/): Mentors: Emanuele Parisi and Ruben Salvador Company: Barcelona Supercomputing Center, INRIA Rennes Control-flow integrity (CFI) is a fundamental security mechanism
- [AI-assisted extraction of architectural parameters from RISC-V specifications – Part II (RISC-V Mentorship)](https://riscv.org/job/ai-assisted-extraction-of-architectural-parameters-from-risc-v-specifications-part-ii-risc-v-mentorship/): Mentor: Ajit Dingankar Company: Qualcomm Technologies Inc. This mentorship proposal extends an effort already underway to extract architectural parameters from
- [Implementation of Tightly-Coupled Data-Flow Integrity in RISC-V (RISC-V Mentorship)](https://riscv.org/job/implementation-of-tightly-coupled-data-flow-integrity-in-risc-v-risc-v-mentorship/): Mentors: Emanuele Parisi and Ruben Salvador Company: Barcelona Supercomputing Center, INRIA Rennes Data-Flow Integrity (DFI) offers robust protection against memory
- [Design Verification Manager](https://riscv.org/job/andes-technology-vancouver-bc-canada-98-design-verification-manager/): Design Verification Manager Vancouver, BC, Canada - Hybrid – onsite 25%-30% of the time and work from home. Senior engineer

## Exchange
- [Renesas FPB-R9A02G021 RISC-V MCU Fast Prototyping Board](https://riscv.org/blog/exchange/renesas-fpb-r9a02g021-risc-v-mcu-fast-prototyping-board/): The FPB-R9A02G021 Fast Prototyping Board provides an entry point for evaluation, prototyping and development with the R9A02G021 MCU. Moreover, since
- [Grande Risco 5](https://riscv.org/blog/exchange/grande-risco-5/): Grande RISCO 5 is a RISC-V RV32IMBC_Zicsr processor with a 5-stage pipeline, developed in just a few days off.
- [RISCY-SEECS](https://riscv.org/blog/exchange/riscy-seecs/): RISCY-SEECS is a 5-stage, single-issue, in-order CPU which implements the 32-bit RISC-V instruction set. It fully implements I, M, A
- [AI Cores](https://riscv.org/blog/exchange/ai-cores/): At OpenMachine, we specialize in high-performance AI engines tailored for your chip, chiplet, RISC-V SoC, ASIC, and FPGA needs. Based
- [Prodigy S8-100 Logic System](https://riscv.org/blog/exchange/prodigy-s8-100-logic-system/): Prodigy S8-100 Logic System with VP1902 leverages AMD Versal™ Premium VP1902 adaptive SoC with 100M ASIC gate capacity, delivers 2x

## Organizations
- [EDGE AI FOUNDATION](https://riscv.org/blog/organizations/edge-ai-foundation/)
- [The Institute of Computing Technology of the Chinese Academy of Sciences (ICT)](https://riscv.org/blog/organizations/the-institute-of-computing-technology-of-the-chinese-academy-of-sciences-ict/)
- [MIT Reality Hack](https://riscv.org/blog/organizations/mit-reality-hack/)
- [hardwear.io](https://riscv.org/blog/organizations/hardwear-io/)
- [GlobalPlatform](https://riscv.org/blog/organizations/globalplatform/)

## Venues
- [NH Hotel Munich East Conference Center](https://riscv.org/venue/nh-hotel-munich-east-conference-center/)
- [Shenzen Convention & Exhibition Center](https://riscv.org/venue/shenzen-convention-exhibition-center/)
- [Universidad Nacional de Córdoba](https://riscv.org/venue/universidad-nacional-de-cordoba/)
- [Prague Congress Centre](https://riscv.org/venue/prague-congress-centre/)
- [Jio World Convention Centre](https://riscv.org/venue/jio-world-convention-centre/)

## Organizers
- [Ultima Media](https://riscv.org/organizer/ultima-media/)
- [CARLA](https://riscv.org/organizer/carla/)
- [IQPC Exhibitions](https://riscv.org/organizer/iqpc-exhibitions/)
- [BSC and 10xEngineers](https://riscv.org/organizer/bsc-and-10xengineers/)
- [Consumer Technology Association](https://riscv.org/organizer/consumer-technology-association/)

## Events
- [AI Infra Summit – RISC-V Pavilion](https://riscv.org/event/ai-infra-summit-risc-v-pavilion/): While at AI Infra Summit, September 15 - 17, 2026 at the Santa Clara Convention Center, visit the RISC-V Pavilion
- [ACC – Automotive Computing Conference](https://riscv.org/event/acc-automotive-computing-conference/): The Gateway to Interactive Learning & Global Networking Driving Innovation in Automotive High-Performance Computing - Where unmatched expertise fuels inspiration
- [RISC-V China Summit](https://riscv.org/event/risc-v-china-summit/): The 6th RISC-V China Summit is coming October 18 - 20 in Shenzen Convention & Convention Center. Call for Papers 
- [CARLA Conference](https://riscv.org/event/carla-conference/): When: September 21 - 25, 2026 Where: Córdoba CARLA is an international conference aimed at providing a forum to foster growth
- [Open Source Summit – Europe](https://riscv.org/event/open-source-summit-europe/): RISC-V will be at Open Source Summit Europe! October 7 - 9 in Prague, Czechia More information coming soon.  

## Categories
- [In the Media](https://riscv.org/blog/category/in-the-media/)
- [Blog](https://riscv.org/blog/category/blog/)
- [News and Updates](https://riscv.org/blog/category/news/): The latest news and updates from around the RISC-V ecosystem.
- [Blog (Chinese)](https://riscv.org/blog/category/blog-chinese/)
- [Uncategorized](https://riscv.org/blog/category/uncategorized/)

## Tags
- [AI](https://riscv.org/blog/tag/ai/): Artificial Intelligence (AI) enables machines to learn, reason, and make decisions. RISC-V empowers AI by providing open, customizable processor designs optimized for neural processing, allowing efficient acceleration of inference and training tasks from edge devices to data centers.
- [Events](https://riscv.org/blog/tag/events/): Our RISC-V Summits, held in Europe, North America and China, are the premier annual events for the ecosystem. They bring together developers, companies, and researchers to share insights, announce innovations, and advance open computing. We also attend major industry events throughout the year.
- [HPC](https://riscv.org/blog/tag/hpc/): High Performance Computing (HPC) refers to using powerful, interconnected processors to solve complex problems quickly. In the RISC-V ecosystem, it means building open, flexible systems that can scale for demanding tasks like scientific research, AI training, and data analysis.
- [Hardware](https://riscv.org/blog/tag/hardware/): RISC-V provides an open foundation for hardware design, enabling custom processors, accelerators, and systems without restrictive licensing. This tag is for original stories that explore the latest RISC-V hardware, from dev boards to data centers.
- [Software](https://riscv.org/blog/tag/software/): Software is the code that tells hardware what to do. RISC-V’s open model fosters broad software support, from compilers to operating systems, driving innovation across all levels of the stack.

## Exchange Categories
- [Software](https://riscv.org/blog/exchange_category/software/)
- [Core](https://riscv.org/blog/exchange_category/core/)
- [Learning](https://riscv.org/blog/exchange_category/learning/)
- [Hardware](https://riscv.org/blog/exchange_category/hardware/)
- [Cores](https://riscv.org/blog/exchange_category/cores/)

## Organization Categories
- [Alliances Industry](https://riscv.org/blog/organizations_category/alliances-industry/)
- [Alliances Regional](https://riscv.org/blog/organizations_category/alliances-regional/)
- [Alliances Technical](https://riscv.org/blog/organizations_category/alliances-technical/)
- [Development Partners](https://riscv.org/blog/organizations_category/development-partners/)

## Event Categories
- [Industry Events](https://riscv.org/events/category/industry-events/)
- [RISC-V Events](https://riscv.org/events/category/riscv-events/)
- [Regional Events](https://riscv.org/events/category/regional-events/)

## Authors
- [RISC-V Community News](https://riscv.org/blog/author/inthenews/)
- [Anisha Sharma](https://riscv.org/blog/author/anisha/)
- [Jeffrey Osier-Mixon](https://riscv.org/blog/author/jefro/)
- [iszheng](https://riscv.org/blog/author/iszheng/)
- [abringaze](https://riscv.org/blog/author/abringaze/)

## Optional
- [Sitemap index](https://riscv.org/wp-sitemap.xml)