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Why RISC-V Will Prevail | Marc Sauter, Golem

By October 21, 2019May 12th, 2021No Comments

At lunch at the RISC-V workshop in Zurich, Krste Asanovic succinctly answers the initial question: “RISC-V is called that because it is our fifth major RISC architecture.” Asanovic must know, because the Berkeley University professor is co-inventor of the Open CPU (Open Hardware ISA) architecture. It was designed in 2010 together with RISC veteran David Petterson and made available in 2014.
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