RISC-V Ecosystem News

Embedded Computing Design Podcast: Five Minutes With…Rick O’Connor, Executive Director, RISC-V Foundation

Last week, the RISC-V Foundation held a workshop in Silicon Valley. The purpose was to update developers on the progress of the technology and also let some of the partners talk about their own developments/products. By most measures, the workshop was deemed a success. I spoke to Rick O’Connor, the Executive Director of the RISC-V Foundation in this week’s Five Minutes with…discussion to see if he agreed. Rick also went…

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Forbes Article: Western Digital Gives A Billion Unit Boost To Open Source RISC-V CPU

Many (likely most) of you have not heard of RISC-V. It’s a new instruction set intellectual property  (IP) that is open sourced and offers an alternative to licensed IP from Arm and MIPS. As instruction sets go, RISC-V is relatively new, having just exited the University of California, Berkeley and entered the market in 2014 and is now managed by the RISC-V Foundation. But in those last 3 years, the…

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DesignNews Article: Western Digital Transitions To RISC-V Open-Source Architecture For Big Data, IoT

RISC-V, the open-source computer core architecture, will be getting a big push from Western Digital in the coming years as the company has pledged to transitioning its own consumption of processors to RISC-V. According to the company Western Digital ships over one billion cores per year, and plans to double that number. And if all goes according to plan, they will all be based on RISC-V.To read more, please visit: https://www.designnews.com/electronics-test/western-digital-transitions-risc-v-open-source-architecture-big-data-iot/96736693957917

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Andes Announces Advanced SoC Development Environment for V5 AndesCore™ N25 And NX25 Processors With Tool Partners

Andes Technology Corporation (TWSE: 6533), the leading Asia-based supplier of compact, low-power, high-performance 32/64-bit embedded CPU cores and a founding member of RISC-V Foundation, today announces the partnership with the world-class tools vendors including Imperas, Lauterbach, Mentor, a Siemens Business, and UltraSoC (in alphabetical order) to bring their system-on-chip (SoC) development environments to Andes V5 processors and the RISC-V community.http://www.andestech.com/news-d.php?cls=1&id=475

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UltraSoC Selected By Microsemi For Growing RISC-V Product Range

UltraSoC today announced that Microsemi, a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, has licensed UltraSoC’s universal analytics and embedded intelligence platform for use in an expanding range of Microsemi products based on the RISC-V open source processor architecture.https://www.ultrasoc.com/ultrasoc-selected-by-microsemi-for-growing-risc-v-product-range/#more-2741

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Intrinsix Cryptographic IP Selected By DARPA For Use In CHIPS Program, Featuring RISC-V Security Processor

Intrinsix Corp., an advanced semiconductor design services firm, announced that its security and cryptographic subsystem IP has been selected by DARPA for implementation into the DARPA CHIPS program. Intrinsix will create a security chiplet based on their IP.  The subsystem IP is also being used as a security solution for commercial applications such as the Internet-of-Things, smart sensors and other connected appliances.https://www.intrinsix.com/blog/intrinsix-cryptographic-ip-selected-by-darpa-for-use-in-chips-program-featuring-risc-v-security-processor

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The Register Article: WDC To Move All Its Stuff To RISC-V Processors, Build Some Kind Of Super Data-Wrangling Stack

Western Digital has grandly announced its will use the open-source RISC-V processor architecture in all future products and “intends to lead the industry transition toward open, purpose-built compute architectures to meet the increasingly diverse application needs of a data-centric world.”To read more, please visit: https://www.theregister.co.uk/2017/12/01/wdc_risc_v_edge_strategy/

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Forbes Article: RISC-V Enables Smart Storage Devices

Western Digital hosted the 7th RISC-V workshop at their Milpitas facility (in one of the old SanDisk buildings). RISC-V is an open instruction set architecture (ISA) based on reduced instruction set computing (RISC) principles. As an open computer architecture, it can be freely used by any person, permitting anyone to design, manufacture and sell RISC-V chips and software. It was initially developed at the University of California, Berkeley.To read more,…

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eWeek Article: How WD Plans to Lead Major Changeover to RISC-V Processing

Talk about going “all in,” and fast. Western Digital, the storage hardware artist formerly known as WD, boldly predicted Nov. 28 that it is going to sell more than 1 billion new RISC-V core processors within the next two years. RISC-V (pronounced “risk-five”) is an open instruction-set computing architecture based on established reduced instruction set computing (RISC) principles. It is an open-source project available to anybody who wants to get involved.To…

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Embedded Computing Design Article: Codasip Releases 64-bit RISC-V Processor

Codasip has released the Bk5-64 Berkelium processor, the company’s first 64-bit implementation of the RISC-V instruction set architecture (ISA). Bk5-64 processors are generated using the Codasip Studio customization tool that allows for fast core configuration and optimization.To read more, please visit: http://www.embedded-computing.com/processing/codasip-releases-64-bit-risc-v-processor

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