RISC-V Ecosystem News

AB Open Article: Researchers Publish Roadmap For RISC-V Opportunities In Space Tech

Researchers at the Delft University of Technology have published a roadmap which seeks to maximize the potential of the open RISC-V instruction set architecture (ISA) for space applications across the full range of requirements from low-power microcontrollers up to high-end payload processors for artificial intelligence applications. To read more, please visit https://abopen.com/news/researchers-publish-roadmap-for-risc-v-opportunities-in-space-tech/.

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Semiconductor Engineering Article: Week In Review: Design, Low Power

Check out upcoming semiconductor conferences and events: Hot Chips will be held Aug. 18-21 at Stanford University, CA, while Western Digital will hold a RISC-V meetup Aug. 21 in Austin, TX. In India, Cadence will host CDNLive Aug. 28-29 in Bengaluru, and Mentor will host its Forum for Verification on Aug. 28 in Bangalore and Aug. 30 in Hyderabad. To read more, please visit https://semiengineering.com/week-in-review-design-low-power-56/.

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News.hqew Article: The Latest Open Source Chip System Level Verification And Prototype Platform Officially Released

The self-developed RISC-V open-source chip design system-level verification and prototype platform SERVE was officially released. It was recently debuted at the 23rd Annual Conference of Computer Engineering and Technology of the Chinese Computer Society, and the 9th “Microprocessor Technology” Forum.According to the China Open Instruction Eco-RISCV Alliance, the SERVE platform is based on the mainstream SoC-FPGA programmable logic devices and boards currently on the market. Compared with the existing RISC-V…

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Phoronix Article: QEMU 4.1 Released With Many ARM, MIPS & x86 Additions

QEMU 4.1 is now out as one of the important pieces to the open-source Linux virtualization stack. On the RISC-V front are the Spike machine model, ISA 1.11 support, and support for CPU topology in device trees. On the x86 front, there is support for new Hygon Dhyana and Intel Snow Ridge CPU models as well as emulation support for the RdRand extension. To read more, please visit https://www.phoronix.com/scan.php?page=news_item&px=QEMU-4.1-Released.

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Forbes Article: Seizing Controllers At The FMS

Flash memory controllers are vital to the operation of an SSD. The 2019 Flash Memory Summit (FMS) featured SSD and even memory controllers from established and start-up companies and supplying a variety of NVMe and DDR4 storage solutions. Fadu, a start-up flash memory company says that low power operation is achieved by putting often used functions on a HW accelerator with small 16-bit controllers and with exceptions handled on its…

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Elektronikne.de Article: RISC-V Roadshow – Guest Performances In Munich And Berlin

A half-day program was compiled by the RISC-V Foundation and the Linux Foundation for their RISC-V Roadshow, “Getting Started with RISC-V” in Europe. In addition to large semiconductor manufacturers such as Microchip and Western Digital, smaller-scale semiconductor manufacturers such as Greenwaves and Trinamic, both from Europe, are participating in the open-source instruction architecture RISC-V.The roadshow program will be rounded off with presentations on embedded software development – from mines –…

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EE Times Taiwan Article: Embedded Processor Faces Side Channel Attack

Until recently, security protection has focused on software stacks, which provide underlying protection such as a root of trust. The RISC-V Foundation focuses on the implementation of security platforms and mechanisms to prevent untrusted code from affecting the integrity of critical system functions. These security features are critical to verifying software updates.Open-source hardware based on the RISC-V ISA provides an opportunity for a higher level of security review. At the same time,…

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Elektronik Praxis Article: RISC-V Foundation Ratifies Specifications For Base And Privileged Architectures

The now validated RISC-V base modules RV32I, RV64I, and RVWMO (RISC-V Weak Memory Ordering) form the basic interface between the application software and the hardware. Developed on the basis of a codified simple instruction set architecture and modular standard extensions, they avoid fragmentation of the platform and keep the door open for future expansion.In addition, they ensure a high degree of interoperability between different implementations. By releasing the specifications for…

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Packt Article: Red Hat Joins The RISC-V Foundation As A Silver Level Member

Last week, RISC-V announced that Red Hat is the latest major company to join the RISC-V foundation. Red Hat has joined as a Silver level member, which carries $5,000 per year, including 5 discounted registrations for RISC-V workshops.RISC-V is a free and open-source hardware instruction set architecture (ISA) which aims to enable extensible software and hardware freedom in computing design and innovation. As a member of the RISC-V Foundation, Red Hat now…

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Linux Magazin.de Article: Red Hat Joins RISC-V-Foundation

Red Hat is now officially joining the RISC-V Foundation, following its parent company IBM. With this partnership in place, the company expects to have more control and say in the developing hardware. This also opens up Red Hat to the hundreds of members that are currently part of the Foundation.Red Hat has been working with RISC-V for some time on developing Fedora 28 which also supports RISC-V boards. Transparency has…

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