RISC-V Ecosystem News

NEOX V Announced By Think Silicon As First RISC-V 3D GPU | Michael Larabel, Phoronix

While there has been the Libre RISC-V community-driven effort to create a RISC-V graphics processor that basically amounts to a RISC-V core with vector extensions/improvements and running a Vulkan software implementation (though they are now reportedly eyeing POWER instead of RISC-V), Think Silicon has announced the first actual RISC-V ISA based 3D graphics processor.article: https://www.phoronix.com/scan.php?page=news_item&px=NEOX-V-RISC-V-3D-GPU

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Yadro Takes Control Of Russian RISC-V Startup | Peter Clarke, eeNews Europe

Server and storage company Yadro has taken a controlling interest in Syntacore, a Russian developer of RISC-V processors. Yadro is part of Russia’s IKS Holding JSC (Moscow, Russia) conglomerate and has gained control of St Petersburg based Syntacore JSC. The move will allow further integration of a Russian supply and manufacturing chain for servers and data storage products. Russia is pushing to end the use of Intel and AMD processors…

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An open source SystemVerilog Test Suite | Antmicro

At Antmicro, we work with improving development flows for both software, hardware, FPGA and ASIC design, for which we use, contribute to and produce a wide variety of open source tools.article: https://antmicro.com/blog/2019/11/systemverilog-test-suite/

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Antmicro Exhibits At RISC-V Summit 2019: Renode, Fomu And Open Chip Design

RISC-V Foundation Platinum Founding Member Antmicro will be exhibiting at RISC-V Summit 2019, the annual global conference for the disruptive open ISA that is paving the way for open digital design. The show will be hosted in the San Jose Convention Center, California, from December 10th to 12th, and as always, Antmicro is announcing a significant presence there.article: https://antmicro.com/blog/2019/11/risc-v-summit-2019/

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SiFive Welcomes Ann Chin As SiFive IP Business Unit General Manager | staff, SiFive

SAN MATEO, Calif., Nov. 26, 2019 /PRNewswire/ — SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, today announced that Ann Chin has joined the company as vice president and co-general manager of the SiFive IP business unit. Chin joins SiFive IP Business Unit Vice President and Co-General Manager Mohit Gupta to ensure the development and execution of next-generation high-performance, scalable processor core IP. SiFive continues to invest in expanding the performance of…

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Getting Started with Embedded Linux on RISC-V in QEMU | Jean-Luc Aufranc, CNX Software

RISC-V is getting more and more popular, but if you want to run Linux on actual hardware it’s currently fairly expensive since you either need to rely on HiFive Unleashed SBC ($999), or expensive FPGAs.Another solution is running Linux RISC-V via QEMU emulator,  and I showed how to do this using BBL (Berkeley Boot Loader),  Linux 4.14, and busybear rootfs. If you check the comments section of that earlier post you could also try…

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Bootlin’s Michael Opdenacker Gets You Started with Embedded Linux on RISC-V in Just 40 Minutes | Gareth Halfacree, AB Open

Building on a presentation first given at the Libre Software Meeting 2005, in which Opdenacker demonstrated how to get Linux 2.6 up and running on a QEMU-emulated Arm device in under 40 minutes, the new presentation was triggered by a range of changes – including the order-of-magnitude reduction in cost of entry-level development boards, increasing popularity of free and open hardware, and most particularly the launch of the free and…

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SparkFun Picks SiFive’s FE310 to Power RISC-V-Based RED-V Thing Plus, RED-V RedBoard Dev Boards | Gareth Halfacree, Hackster.io

SparkFun has officially launched the RED-V Thing Plus and RED-V RedBoard, a pair of Feather-compatible Thing Plus-footprint and Arduino Uno-format development boards based on the SiFive Freedom E310 RISC-V microprocessor core — making them, the company claims, “completely open source […] from hardware to ISA.”article: https://www.hackster.io/news/sparkfun-picks-sifive-s-fe310-to-power-risc-v-based-red-v-thing-plus-red-v-redboard-dev-boards-c321292f9781

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Imperas delivers highest quality RISC-V RV32I compliance test suites to implementers and adopters of RISC-V

Imperas developed compliance tests quantified by open source collaboration of verification coverage tools developed by Google CloudOxford, United Kingdom, November 26, 2019 — Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced the release of the latest update to the RISC-V compliance test suite for RV32I base RISC-V configuration. Developed in conjunction with the RISC-V Foundation’s Technical Committee task group for compliance, Imperas has achieved…

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Semico Forecasts Strong Growth for RISC-V

Semico forecasts strong growth for RISC-V, predicting the market will consume 62.4 billion RISC-V CPU cores by 2025San Francisco – Nov. 25, 2019 – The RISC-V Foundation, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), today announced that Semico Research’s new report “RISC-V Market Analysis: The New Kid on the Block” estimates that the market…

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