RISC-V Ecosystem News

Lauterbach and SiFive Bring TRACE32 Support for High-Performance RISC-V Cores

Lauterbach, the leading manufacturer of microprocessor development tools, and SiFive, the first fabless provider of customized, open-source-enabled semiconductors, announced the availability of Lauterbach’s TRACE32 toolset to provide debug capabilities for SiFive’s E31 and E51 RISC-V Core IP, based on the free and open RISC-V ISA. https://www.sifive.com/posts/2017/10/24/lauterbach-and-sifive-bring-trace32-support-for-high-performance-risc-v-cores/ 

Read More...

EE Journal Article: The People’s Processor, Microsemi Rolls Out “Mi-V” RISC-V Ecosystem

The capitalist computing bourgeoisie want to enslave us all with proprietary processing architectures, but the proletariat eventually produces its own processor alternative – an ISA for and by the people, where instruction sets aren’t subject to the whim of the royalty-driven class, and where licensing fees don’t oppress the workers’ BOMs. RISC-V is that ISA – the people’s processor, the unmoving, unwavering instruction set whose implementation carries no fees or…

Read More...

Electronic Design Article: RISC-V FPGA Design Leaps Forward with Mi-V

A longtime supporter of the RISC-V (pronounced RISC Five) instruction set architecture (ISA), Microsemi provides tools and RISC-V soft cores for its various FPGA lines, including the recently unveiled Mi-V (pronounce My Five) ecosystem. Mi-V further streamlines RISC-V development by giving software developers a starting point that’s able to bypass the FPGA design process, while offering FPGA developers an easier starting point for RISC-V-based designs.To read the full article, please visit: http://www.electronicdesign.com/embedded-revolution/risc-v-fpga-design-leaps-forward-mi-v

Read More...

RISC-V E-Newsletter October 2017

Click HERE to Join the RISC-V Foundation Mail ListsAs we are gearing up for the 7th RISC-V Workshop, hosted by Western Digital in Milpitas, Calif. from Nov. 28 to Nov. 30, 2017, we have been thrilled to see the influx of submissions for talks and poster presentations. We are excited to unveil the full agenda which you can view here. The first two days of the event are packed with…

Read More...

Microsemi Launches Mi-V Ecosystem to Accelerate Adoption of RISC-V

Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced the company’s new Mi-V™ ecosystem with industry leaders, to increase adoption of its RISC-V soft central processing unit (CPU) product family.https://investor.microsemi.com/2017-10-19-Microsemi-Launches-Mi-V-Ecosystem-to-Accelerate-Adoption-of-RISC-V

Read More...

7th RISC-V Workshop Showcases Breadth of the RISC-V Ecosystem with More Than 45 Sessions Featuring Technology Leaders

Attendees will learn about notable RISC-V updates, projects and implementations across the globeWHAT: 7th RISC-V WorkshopWHERE: Western Digital, 951 Sandisk Dr., Milpitas, Calif. 95035, Building 2WHEN: Tuesday, Nov. 28 to Thursday, Nov. 30, 2017DETAILS: The RISC-V Foundation is hosting the 7th RISC-V Workshop, bringing its expansive, international ecosystem together to discuss current and prospective RISC-V projects and implementations, as well as collectively drive the future evolution of the instruction set…

Read More...

Design News Article: Linux Now Has its First Open Source RISC-V Processor

With its new, first-of-its-kind Linux-compatible multi-core CPU, SiFive is moving to pushing the open source RISC-V architecture into an expanded world of use cases, including machine learning and IoT.SiFive has declared that 2018 will be the year of RISC V Linux processors.When it released its first open-source system on a chip, the Freeform Everywhere 310, last year, Silicon Valley startup SiFive was aiming to push the RISC-V (“risk five”) architecture to transform…

Read More...

RISC-V Ecosystem to Present at 15th International System-on-Chip (SoC) Conference, Exhibit & Workshops

Six Companies from the RISC-V Ecosystem to Host Speaking Sessions at Conference WHERE:The 15th International System-on-Chip (SoC) Conference, Exhibit & Workshops, University of California, Irvine (UCI) , Irvine, Calif., 92697, Calit2 Building 2 WHEN:Wednesday, Oct. 18 to Thursday, Oct. 19, 2017 WHAT:The RISC-V Foundation will feature six member organizations at this year’s International SoC Conference. Ted Speers, VP and Head of Product Architecture and Planning for Microsemi SoC Group, a…

Read More...

RISC-V Ecosystem to Showcase New Implementations of RISC-V ISA at Linley Processor Conference 2017

RISC-V Members Including Codasip, Dover Microsystems, Imperas, Microsemi and SiFive to Demo New Innovative Products Based on Open, Free RISC-V ISA WHERE:Linley Processor Conference 2017, Hyatt Regency Santa Clara, 5101 Great America Pkwy, Santa Clara, Calif., 95054 WHEN:Wednesday, Oct. 4 to Thursday, Oct. 5, 2017 WHAT:The RISC-V Foundation, together with members including Codasip, Dover Microsystems, Imperas, Microsemi and SiFive, will exhibit new RISC-V implementations at the Linley Processor Conference 2017….

Read More...