RISC-V News

RISC-V Draft Privileged Architecture Version 1.7 Released

The RISC-V Privileged Architecture Draft Specification has been released and is available at: /specifications/privileged-isa/.This is only a proposal at this point, and we welcome community feedback and comments on this draft. Please participate in the discussion on the public sw-dev and hw-dev RISC-V mailing lists, to which you can subscribe on the www.riscv.org website. We hope to freeze the core parts of this privileged architecture specification later this year.We will very shortly be releasing an updated Spike…

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RISC-V github organization

With RISC-V expanding beyond just UC Berkeley, we have moved out most of the RISC-V software stack to a separate “riscv” github organization. Generally speaking, the repositories that fall into the new “riscv” github organization are things that are staged for upstreaming (e.g. gcc, llvm, qemu, etc). This is hence why the rocket-chip-related infrastructure is staying in the “ucb-bar” github organization.Here’s an excerpt from https://help.github.com/articles/transferring-a-repository on further information regarding repositories that are…

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A Linux Distribution for RISC-V

We are excited to announce the release of riscv-poky, a full Linux Distribution for RISC-V. The distribution is a port of the Yocto Project, a major Linux distribution targeted at embedded systems and known for its portability and powerful build process. Yocto is a workgroup within the Linux Foundation, and is supported by a number of major industrial partners such as Broadcom, Intel and Texas Instruments. While a RISC-V Linux…

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Announcing the RISC-V GCC 4.9 port and new ABI

We are excited to announce our release of a new, clean-slate port of gcc 4.9 to RISC-V.  The riscv-tools repository has been updated to reflect the use of our new gcc port in the master branch.   There are a couple differences to be aware of. First, the compiler binary name has changed to follow GNU conventions (riscv-gcc is now riscv64-unknown-elf-gcc, or riscv64-unknown-linux-gnu-gcc for the Linux/glibc variant).  Second, the riscv-gcc…

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Get Answers On Stack Overflow!

We now have a new Stack Overflow for RISC-V questions.To help lessen some of the technical support and troubleshooting questions that have been popping up on the mailing lists, we have added a “riscv” tag to http://stackoverflow.com/tags/riscv/.  This has a couple of advantages.  It reduces the traffic related to toolchain difficulties so we do not inundate users who want to discuss RISC-V at a more general level; it provides a Google-able…

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Launching the Open-Source Rocket Chip Generator!

We are very excited to announce the alpha release of our Rocket chip generator. This generator toolkit can be used to create instances of our high-performance, energy-efficient Rocket processor suitable for both high-speed simulation and full synthesis. We have provided a collection of components that go well beyond simple pipeline RTL in order to allow you to generate a complete Rocket implementation, including a memory subsystem. What is Rocket? Rocket is a 5-stage…

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RISC-V Analysis by Adapteva Founder

Andreas Olofsson is the founder of Adapteva and the creator of the Epiphany architecture and Parallella open-source computing project.  He has published his own analysis of the RISC-V ISA. Quoting the conclusion:“The RISC-V architecture is not revolutionary, but it is an excellent general purpose architecture with solid design decisions. The true breakthrough here is really the open source licensing model and the maturity of the design as compared to most other open…

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ARM’s rebuttal to RISC-V: “The Case for Licensed Instruction Sets”

MICROPROCESSOR Report has publicly released an extended version of our technical report “Instruction Sets Should Be Free: The Case For RISC-V” and ARM’s corresponding rebuttal.  The RISC-V publication webpage has been updated with the following links: The Case for Open Instruction Sets, by Krste Asanovic and David Patterson, UC Berkeley The Case for Licensed Instruction Sets, by Ian Smythe and Ian Ferguson, ARM

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