RISC-V News

Charting a New Course for Semiconductors

The Global Semiconductor Alliance has released a new report “Charting a New Course for Semiconductors” which explores the future of the semiconductor industry and asks “Is RISC-V the new Linux?”.                               Global Semiconductor Alliance Releases New ReportThe report includes 4 Chapters covering key areas including: Chapter 1 – An Industry in Transition – Rising development costs, decreasing margins and…

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RISC-V Draft Compressed ISA version 1.9 released

The RISC-V Compressed Instruction Set Manual Version 1.9 Draft proposal has been released and is available at this link.  You can also download a PDF version at this link.We welcome community feedback and comments on this draft. We believe this draft represents the close to final design for RV32C and RV64C (it seems premature to freeze R128C), though we are requesting one more round of comments, hence the 1.9 revision…

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RISC-V in Verilog

V-scale, an implementation of an RV32IM core in Verilog has been released and is available at: https://github.com/ucb-bar/vscale.This core implements a simple, Z-scale-class pipeline, and is designed for integration with either existing microcontroller-class bus interconnects or the Rocket chip generator. The build infrastructure for both flows will be publicly released with an upcoming update to the platform of small RISC-V systems compatible with Z-scale.

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RISC-V Foundation Incorporated!

The RISC-V Foundation has been officially incorporated! For more information about joining the RISC-V Foundation, please contact Rick O’Connor, Executive Director via email at rickoco@riscv.org.

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RISC-V Draft Compressed ISA Version 1.7 Released

The RISC-V Compressed Instruction Set Manual Version 1.7 Draft proposal has been released and is available at this link. You can also download a PDF version at this link.We welcome community feedback and comments on this draft. In particular, we offer two options of what RVC should be. Thus, we need your feedback in order to decide which path to take. (The report lists the pros and cons of each…

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RISC-V Draft Privileged Architecture Version 1.7 Released

The RISC-V Privileged Architecture Draft Specification has been released and is available at: /specifications/privileged-isa/.This is only a proposal at this point, and we welcome community feedback and comments on this draft. Please participate in the discussion on the public sw-dev and hw-dev RISC-V mailing lists, to which you can subscribe on the www.riscv.org website. We hope to freeze the core parts of this privileged architecture specification later this year.We will very shortly be releasing an updated Spike…

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RISC-V github organization

With RISC-V expanding beyond just UC Berkeley, we have moved out most of the RISC-V software stack to a separate “riscv” github organization. Generally speaking, the repositories that fall into the new “riscv” github organization are things that are staged for upstreaming (e.g. gcc, llvm, qemu, etc). This is hence why the rocket-chip-related infrastructure is staying in the “ucb-bar” github organization.Here’s an excerpt from https://help.github.com/articles/transferring-a-repository on further information regarding repositories that are…

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A Linux Distribution for RISC-V

We are excited to announce the release of riscv-poky, a full Linux Distribution for RISC-V. The distribution is a port of the Yocto Project, a major Linux distribution targeted at embedded systems and known for its portability and powerful build process. Yocto is a workgroup within the Linux Foundation, and is supported by a number of major industrial partners such as Broadcom, Intel and Texas Instruments. While a RISC-V Linux…

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Announcing the RISC-V GCC 4.9 port and new ABI

We are excited to announce our release of a new, clean-slate port of gcc 4.9 to RISC-V.  The riscv-tools repository has been updated to reflect the use of our new gcc port in the master branch.   There are a couple differences to be aware of. First, the compiler binary name has changed to follow GNU conventions (riscv-gcc is now riscv64-unknown-elf-gcc, or riscv64-unknown-linux-gnu-gcc for the Linux/glibc variant).  Second, the riscv-gcc…

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