RISC-V Ecosystem News

Reduced Energy Microsystems Joins FDXcelerator Program To Bring RISC-V IP To GLOBALFOUNDRIES’ 22FDX Technology Process

Reduced Energy Microsystems (REM) announced today that it has joined GLOBALFOUNDRIES’ FDXcelerator™ Partner Program, and will be making RISC-V CPU IP available for GF’s 22FDX® process. Based around the open source RISC-V ISA, REM’s IP will offer a low-power core to be integrated into future SoCs to be used across a range of verticals.https://www.design-reuse.com/news/43234/reduced-energy-microsystems-fdxcelerator-risc-v-ip-globalfoundries-22fdx.html

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Forbes Article: Western Digital Gives A Billion Unit Boost To Open Source RISC-V CPU

Many (likely most) of you have not heard of RISC-V. It’s a new instruction set intellectual property  (IP) that is open sourced and offers an alternative to licensed IP from Arm and MIPS. As instruction sets go, RISC-V is relatively new, having just exited the University of California, Berkeley and entered the market in 2014 and is now managed by the RISC-V Foundation. But in those last 3 years, the…

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Tom’s Hardware Article: RISC-V Foundation Trumpets Open-Source ISAs In Wake Of Meltdown, Spectre

The RISC-V Foundation says that no currently announced RISC-V CPU is vulnerable to Meltdown and Spectre and, in the wake of those bugs, stressed the importance of open-source development and a modern ISA in preventing vulnerabilities.In consumer computing, we usually only hear about two instruction set architectures (ISA): x86 and ARM. Classified as a complex instruction set, x86 dominates the desktop and server space. Since the rise of smartphones, however, reduced-instruction-set…

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Building a More Secure World with the RISC-V ISA

Krste Asanović, Chairman, RISC-V Foundation Rick O’Connor, Executive Director, RISC-V FoundationRecent articles in the media have raised awareness around the processor security vulnerabilities named Meltdown and Spectre. These vulnerabilities are particularly troubling as they are not due to a bug in a particular processor implementation, but are a consequence of the widespread technique of speculative execution. Many generations of processors with different ISAs and from several different manufacturers are susceptible…

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AB Open Article: Esperanto Announces 4,112-Core RISC-V AI Chip

Detailed in full on WikiChip Fuse, Esperanto’s aim is to produce three intellectual property (IP) core families based on the open RISC-V architecture: ET-Maxion, a high-performance core designed as an alternative to Arm; ET-Minion, a high-efficiency core; and ET-Graphics, the first RISC-V-based graphics processor. Each will be implemented on Taiwan Semiconductor (TSMC)’s 7nm process node, the company has claimed, and will be available in hardware and licensable IP forms.To read more,…

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Semiconductor Engineering Article: Reflection On 2017: Design And EDA

People love to make predictions, and most of the time they have it easy, but at Semiconductor Engineering, we ask them to look back on the predictions they make each year and to assess how close to the mark they were. We see what they missed and what surprised them. Not everyone accepts our offer to grade themselves, but most have this year. (Part one looked at the predictions associated with…

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Seeking Alpha Article: Benchmark: WDC, NVDA Adding Fuel To RISC-V Movement

A new innovation in computer chip architecture is taking hold, Benchmark notes, and it could be “disruptive” for traditional processors (and a possible boon to companies getting on board).RISC-V is the latest version of the “reduced instruction set” architecture, a more modifiable system allowing for more customer tailoring of silicon, and a note from Benchmark’s Gary Mobley highlights what’s going on in the area.To read more, please visit: https://seekingalpha.com/news/3320988-benchmark-wdc-nvda-adding-fuel-risc-v-movement

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Barron’s Article: Western Dig, Nvidia On Board with ‘RISC-V,’ So Pay Attention, Says Benchmark

If you like semiconductors, you should really check out this “RISC-V” thing, according to a missive today from Gary Mobley of The Benchmark Company. RISC-V, in case you don’t know, is the latest incarnation of the “reduced instruction set computing” architecture, devised by Professor David Patterson of U.C. Berkeley about 40 years ago. I interviewed Patterson about RISC-V last summer for Barron’s print magazine. The notion is that by making the “instruction-set architecture,” or ISA, of a chip more like open source, where…

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Electronic Design Article: These 2017 Embedded Trends Will Thrive in 2018

Trends rarely follow yearly boundaries, and many significant trends hang around for a long time. What follows are those that emerged last year, and continue to grow in importance in the embedded space.RISC-V is an instruction-set architecture. That’s important because RISC-V requires a hardware implementation to be usable, but it doesn’t define an implementation. The standard actually defines a set of features that can be combined and implemented in hardware,…

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Semiconductor Engineering Article: Reflections On 2017: Manufacturing And Markets

People love to make predictions, and most of the time they have it easy, but at Semiconductor Engineering, we ask them to look back on the predictions they make each year and to assess how close to the mark they were. To see what they missed and what surprised them. Not everyone accepts our offer to grade themselves, but many have this year. This is the first of two parts…

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