RISC-V Ecosystem News

Are Open Source RISC-V CPUs Destined For The Server Market? | Christine Hall, IT Pro

One thing that was evident at the December 2019 RISC-V Summit in San Jose, Calif., is that the RISC-V open source instruction set architecture, meant for designing and manufacturing silicon chips, is a rising star in the hardware world. The big question right now is whether the project will forever remain in the CPU-helper space it currently occupies, or will we be seeing RISC-V CPUs being deployed in data center…

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RISC-V Business: SiFive And CEVA Join Forces To Enable The Development AI-Amenable, Edge-Oriented Processors | Thomas Claburn, The Register

On Tuesday, RISC-V CPU fixer SiFive announced it’s working with CEVA, which licenses technology for deep learning, audio, and computer vision, to simplify the creation of processors capable of handling machine learning code without demanding too much power.article: https://www.theregister.co.uk/2020/01/08/riscv_sifive_ceva/

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SiFive And CEVA Partner To Bring Machine Learning Processors To Mainstream Markets

SAN MATEO and MOUNTAIN VIEW, Calif., Jan. 7, 2020 /PRNewswire/ — SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions and CEVA, Inc. (NASDAQ: CEVA), the leading licensor of wireless connectivity and smart sensing technologies, today announced a new partnership to enable the design and creation of ultra-low-power domain-specific Edge AI processors for a range of high-volume end markets. The partnership, as part of SiFive’s DesignShare program, is centered around RISC-V CPUs,…

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10 Leading Tech Trends: How Artificial Intelligence Will Evolve In The Coming Year | DataQuest

The traditional model of chip design cannot efficiently respond to the fast evolving, fragmented and customized needs of chip production. The open source SoC chip design based on RISC-V, high-level hardware description language, and IP-based modular chip design methods have accelerated the rapid development of agile design methods and the ecosystem of open source chips. In addition, the modular design method based on chiplets uses advanced packaging methods to package…

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Defense-Grade FPGA Debuts With Early Access | Gina Ross, Embedded.com

Delivering defense-grade security to embedded systems at the edge, Microchip Technology Inc. offers an early access program (EAP) for the PolarFire SoC FPGA. This platform is the first hardened real-time, Linux capable, RISC-V-based microprocessor subsystem on the mid-range PolarFire FPGA family. This platform can be used in communications, defense, medical, and industrial automation applications.The chip is the industry’s first SoC FPGA with a deterministic, coherent RISC-V CPU cluster and a deterministic…

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Week In Review: Design, Low Power | Jesse Allen, Semiconductor Engineering

Bluespec debuted its RISC-V Factory tool suite aimed at helping speed development and verification of a variety of RISC-V based cores, including users’ proprietary cores, third party proprietary cores, and open source cores. It provides an IP management capability that allows users to package, document, and debug, while also delivering software tool chains. Additionally, a development environment for the cores provides application and system software that allows for the addition of hardware…

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Polos GD32V Alef Is A Tiny RISC-V MCU Board Selling For $3 | Jean-Luc Aufranc, CNX Software

We first found out about GigaDevice GD32V 32-bit RISC-V MCU last summer, as an update/alternative to the earlier STM32 compatible GD32 Arm Cortex-M3 microcontroller from the company with higher performance and lower power consumption, while keeping the price identical.The first low-cost GD32V development board we covered was Longan Nano going for $5 with an OLED display and an acrylic case. If you don’t need either or want to access all pins from the 48-pin MCU,  you…

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RISC-V Lagarto Is First Open Source Chip Developed In Spain | Rich Brueckner, insideHPC

The Barcelona Supercomputing Center has coordinated the manufacture of the first open source chip developed in Spain. Built with TSMC’s 65-nanometer transistors, their RISC-V based Lagarto chip a key step in the center’s strategy to become a benchmark in the open source hardware technologies’ field developed in Europe.article: https://insidehpc.com/2019/12/risc-v-lagarto-is-first-open-source-chip-developed-in-spain/

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