RISC-V Ecosystem News

AB Open Article: Western Digital Boasts Of “Gratifying” SweRV Response, Releases FPGA Reference Design

Western Digital has announced a strong response to the release of its RISC-V based open silicon SweRV Core, along with the availability of an official implementation for field-programmable gate array (FPGA) use.Announced back in December 2018 as part of a company-wide initiative to transition data processing products away from proprietary cores to alternatives based on the RISC-V instruction set architecture (ISA), released in January this year, and the subject of…

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Prohardver Article: Multi-Sheet Experimental Design Was Designed By NVIDIA To Scale Machine Learning

The IT industry has been struggling for some time with the slowdown of Moore’s law. Although the statement itself could still be true today, the cost of newer manufacturing technologies is very high, and the benefits of many physics laws mean that benefits are getting smaller and it is no longer economically viable to keep Moore’s law alive; at least in the traditional way. Nevertheless, companies are typically resourceful, so if a problem cannot be solved,…

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China Times Article: Jingxin Branch Held RISC-V Forum In May To Promote Open Source Instruction Set Architecture

CPU Zhizhicai of the Jingxin Branch strongly promoted the open source instruction set architecture (ISA) RISC-V. To strengthen the industry’s cooperation on RISC-V, the RISC-V CON Forum will be held on May 9, 2019 to expand potential RISC-V customers.The open source instruction set architecture RISC-V has sprung up in recent years and has evolved into a new generation of mainstream embedded processor technology with a rich ecosystem and growing emerging applications. Crystal Science,…

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Electronics Lab Article: SiFive Launches The World’s Smallest Commercial 64-Bit Embedded Core

SiFive, the leading provider of commercial RISC-V processor IP, yesterday announced the launch of the S2 Core IP Series at the Linley Spring Processor Conference in Santa Clara. The S2 Core IP Series is a 64-bit addition to SiFive’s 2 Series Core IP and brings advanced features to SiFive’s smallest microcontrollers. The S2 Series further adds to SiFive’s extensive, vastly customizable, optimized, silicon-proven, embedded core IP portfolio, which comprises the…

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Bit-tech Article: Synaptics Announces Shift To RISC-V Processors

Synaptics, best known for making the touchpads which grace the overwhelming majority of the world’s laptops, has become the latest big-name company to telegraph a move to the burgeoning RISC-V instruction set architecture (ISA), in partnership with SiFive.Designed to offer an open alternative to proprietary instruction set architectures (ISAs) in fields as diverse as ultra-low power embedded and high-performance compute, the permissively-licensed RISC-V is drawing considerable attention of late. As…

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Semiconductor Engineering Article: More Memory And Processor Tradeoffs

Creating a new chip architecture is becoming an increasingly complex series of tradeoffs about memories and processing elements, but the benefits are not always obvious when those tradeoffs are being made.This used to be a fairly straightforward exercise when there was one processor, on-chip SRAM and off-chip DRAM. Fast forward to 7/5nm, where chips are being developed for AI, mobile phones and servers, and there are hundreds or even thousands…

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EE Journal Article: When Tubes Were Better Than Transistors

The Electron Tube Information Council’s tube-versus-transistor book predates publication of Clayton Christensen’s “The Innovator’s Dilemma” by 37 years. Christensen focused his book on disruptive innovation and the idea that new, lower-cost technologies replace established ones somewhat slowly. At first, these new technologies appeal to only those developers who are locked out of a market or markets because of the high cost of existing components needed to do the job.This book…

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CNX Software Article: SiFive S2 RISC-V Core May Be The World’s Smallest 64-Bit Embedded Core

Last year, SiFive introduced their first RISC-V cores competing with Arm Cortex-R family of processors thanks to their S7 Series 64-bit RISC-V Core IP providing an answer to Arm Cortex-R7/R8 32-bit real-time processors.The company has now announced the SiFive S2 RISC-V core that it claims to be the world’s smallest 64-bit embedded core, and also the first SiFive IP core without any direct competitive equivalent in the market. To read more,…

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AB Open Article: RISC-V Foundation Finalizes Schedule For RISC-V Workshop Zurich

The RISC-V Foundation has released the agenda for its RISC-V Workshop Zurich, to be held on the 11th-13th of June as part of the larger Week of Open Source Hardware (WOSH).Following its call for speakers, which closed back in February, the RISC-V Foundation has firmed up the schedule for the three-day RISC-V Workshop Zurich 2019 – though only the first two of these days are open to the general public, with…

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SiFive Tapes Out First In A Series Of 7nm IP Enablement Platforms

SiFive, the leading provider of commercial RISC-V processor IP and custom SoC solutions, today announced it has successfully taped out an IP enablement platform in 7nm FinFET technology that includes critical IP validation for SiFive’s high bandwidth memory (HBM2E) 3.2Gbps interface, 2GHz Ternary Content-Addressable Memory (TCAM) partner IP, a low-voltage differential signaling (LVDS) interface and other key IP building blocks. The high-speed IP interface enablement platform is the first in a…

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