RISC-V Ecosystem News

Embedded Computing Design Article: X-FAB, Efabless Release First Silicon of “Raven” RISC-V SoC

X-FAB and Efabless Corporation have announced first-silicon availability of Raven, an open-source SoC reference design based on the PicoRV32 RISC-V core. A mixed-signal SoC, nearly 75 percent of Raven’s die area leverages X-FAB analog IP and standard macros. Simulations project a maximum clock speed of 150 MHz. To read more, please visit: http://bit.ly/2Rhkqop. 

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EENews Europe Article: X-FAB Silicon Foundries Tapes-Out Open-Source RISC-V MCU

Together with crowd-sourcing IC platform partner Efabless Corporation, X-FAB Silicon Foundries has announced the first-silicon availability of the Efabless RISC-V System on Chip (SoC) reference design. This open-source semiconductor project went from design start to tape-out in less than three months using the Efabless design flow based on open-source tools. The mixed-signal SoC, called Raven, is based on the community developed ultra-low power PicoRV32 RISC-V core.  Efabless has bench-tested the…

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Semiconductor Engineering Article: Week In Review: Design, Low Power

Andes Technology debuted its RISC-V FreeStart program, which makes the company’s N22 RISC-V CPU IP core available to download with no license fee; a royalty is charged for commercial production. The N22 is a small, 2-stage pipeline 32-bit RV32I/EMAC RISC-V CPU core and is integrated with interrupt controller, local memory, instruction cache, debug support, and an optional AHB platform. To read more, please visit: https://semiengineering.com/week-in-review-design-low-power-47/

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Leiphone Article: Berkeley Hands In Tsinghua To Set Up RIOS Laboratory, RISC-V Is Expected To Upgrade To The Most Advanced Level?

UC Berkeley honorary professor David Patterson announced at the RISC-V Summit that he will set up a RISC-V International Open Source Laboratory (RIOS Laboratory) dedicated to RISC-V research. The laboratory is located at the Tsinghua-Berkeley Shenzhen Institute (TBSI) jointly established by the University of California at Berkeley and Tsinghua University.Professor David Patterson is the first expert to propose the “Reduced Instruction Set” (RISC) system. He is currently an honorary professor…

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EEFocus Article: Huami Technology: Huangshan No. 1 Chip Is Currently Using The Future Or Open Cooperation

On June 11th, Huami Technology held a new product launch conference this afternoon. The company released two new products, AMAZFIT Mi Healthy Watch and AMAZFIT Smart Watch. Both products are equipped with Huami Technology’s release of AI chip Huangshan No. 1 last year, marking the official commercialization of its self-developed AI chip. According to the official introduction, the modular Huangshan No. 1 data using the RISC-V architecture can be run inside the device to avoid the communication delay of cloud computing. To read more,…

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Sina Article: Qualcomm Invests Heavily In RISC-V Companies

Qualcomm announced yesterday that it invested $65.4 million in SiFive, a leading provider of IP and silicon solutions for commercial RISC-V processors. In addition to Qualcomm, Intel and Samsung also invested some money in SiFive.Some analysts say Qualcomm is interested in the flexibility and openness of RISC-V. It is reported that according to SiFive’s current design capabilities, it takes only one to three months to develop a new RISC-V IP while…

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TechRadar Article: Security Is Now A Board Level Issue: How To Secure The Data Supply Chain

Hardware security can be provided via a root of trust embedded into a chip that is part of the system as a secure IP core, or by adding a separate dedicated security chip. In most designs, security should be embedded in the main chip in the IoT device, such as an application processor or custom ASIC, to deliver optimal levels of security performance. Our own approach to embedding hardware security…

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EET India Article: Embedded Benchmark Needs Support

EmBench aims to deliver a single performance score based on a suite of about 20 real-world applications, mainly sourced from an earlier effort, the Bristol/Embecosm Embedded Benchmark Suite (BEEBS). It also plans to report metrics for code size and latency but not floating-point performance or power consumption.Figures will generally be reported based on a geometric mean and geometric standard deviation to a reference platform. It tentatively picked PULP RI5CY, an open-source…

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EETimes Article: Andes Technology Launches FreeStart To Boost RISC-V Adoption

What’s clear from listening to the community here at the RISC-V Workshop at ETH in Zurich is that the architecture is still in its infancy and a handful of companies is trying very hard to boost adoption, and convince developers of the benefits of the technology.It’s no surprise then to see the launch of a program encouraging designers to try RISC-V for free, in other words no license fee.  Andes Technology Corporation…

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all-electronics.de Article: OpenHW Group Develops Open Source Cores For SoCs

The OpenHW Group is a non-profit organization similar to the RISC-V Foundation. It aims to increase the adoption of open source processors by providing a collaborative platform, creating a hub for ecosystem development and offering open source IP for processor cores.Under the direction of founder and CEO Rick O’Connor, the organization has already won several sponsors. Sponsors include Alibaba, Bluespec, CMC Microsystems, Embecosm, ETH Zurich, GreenWaves, Imperas, Metrics, Mythic AI, NXP, Onespin,…

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