RISC-V Ecosystem News

RISC-V Foundation Announces Agenda For RISC-V Workshop In Chennai

Workshop features more than 20 speaking sessions and a keynote from Western Digital WHAT: RISC-V Workshop in Chennai, IndiaWHERE: IC&SR Building, Indian Institute of Technology (IIT) Madras, Sardar Patel Road, Opposite to C, L.R.I, Adyar, Chennai, Tamil Nadu 600036, IndiaWHEN: Wednesday, July 18 and Thursday, July 19, 2018DETAILS: The RISC-V Workshop in Chennai will showcase the expansive RISC-V ecosystem, highlighting current and prospective projects and implementations that influence the future evolution…

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EDA Café Interview of Rick O’Connor at DAC 2018

Sanjay Gangal from EDA Café interviews RISC-V Foundation Executive Director Rick O’Connor at DAC 2018. In the interview, the two discuss the beginning of the RISC-V ISA, the Foundation’s presence at DAC and participation of the member companies, current developments of the ecosystem today and plans for the future. To watch the full video, please visit: https://www10.edacafe.com/video/RISC-V-Rick-O39;connor-Executive-Director/616716/media.html

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Top 500 Article: European Program To Develop Supercomputing Chips Begins To Take Shape

The European Processor Initiative (EPI), an ambitious program to develop a pair of chips for domestic supercomputers, is poised to change the way Europe does HPC. And although the work is still very much in its early stages, it looks like the Europeans have selected their preferred processor architectures: Arm and RISC-V.Launched in March 2018 by the European Commission, the EPI’s overall aim is to develop domestically produced low-power microprocessors for…

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Phoronix Article: Ada Language Support For RISC-V With Latest GCC Patches

While the GCC compiler merged its RISC-V port last year, among its limitations have been not supporting the Ada compiler. That’s now changing thanks to new patches posted today.Jim Wilson of SiFive, the company behind the initial HiFive Unleashed RISC-V development board, discovered it was easy getting Ada support for the royalty-free CPU instruction set architecture. This is among other GCC improvement efforts at the company, like getting native GDB debugger…

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Antmicro: Renode 1.4 Released: 64-bit RISC-V HiFive Unleashed Support, Multiple Silicon Labs Targets, And More

With the build-up to the RISC-V Workshop in Barcelona, and our continued partnership with Microsemi to elevate Renode as the industry’s tool of choice for RISC-V development, we are happy to say that the announced support for multi-core 64-bit, Linux-enabled RISC-V targets – along with a multitude of other new features – is now available in Renode’s milestone 1.4 release.RISC-V – Freedom and Unleashed, and anything you’d likeThrough our collaboration with Microsemi, SiFive and…

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Sensors Online Article: Partners Support Agile RISC-V SoC Design Platform With NoCs

Sonics, Inc., supplier of on-chip network (NoC) and power management technologies and services, is partnering with SiFive to enable an agile RISC-V design platform for systems-on-chip (SoC) by making the Sonics’ NoCs interoperable with SiFive’s family of RISC-V Core IP. Sonics’ NoCs are said to be the IP industry’s most widely adopted commercial interconnect fabric and have been shipped in billions of SoCs over the past 20 years. SiFive’s Core…

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RISC-V Foundation Announces Security Standing Committee, Calls Industry To Join In Efforts

Growing Security Standing Committee Features 25 Member Organizations Collaborating to Secure the Future of ComputingThe RISC-V Foundation, a non-profit corporation controlled by its members to drive forward the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), today announced the formation of the Security Standing Committee to bring together industry leaders to share findings, develop consensus around best security practices and identify potential security improvements for RISC-V based…

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EE Times Fish Fry Podcast By Amelia Dalton: To The Cloud And Beyond

Watch out! Fish Fry is taking DAC by storm! In this week’s episode of Fish Fry, we tackle of some of biggest themes presented at this year’s show: EDA’s progression to cloud-based design tools, the increased adoption of the RISC-V architecture, and the ever-present IoT. Craig Johnson and Carl Siva (Cadence Design Systems) join us to chat about why now is the right time for the cloud to take off for EDA and some…

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SiliconANGLE Article: China, Blockchain And Chips: Western Digital Looks Beyond Storage

Executives at Western Digital Corp.have a lot on their minds these days. This week, their attention was focused on new additions to the company’s data center portfolio involving object storage, enhanced all-flash arrays and a new hybrid storage server platform. Last week, the company launched new artificial intelligence-equipped drives for surveillance cameras and released a wireless solid-state drive geared for the travel industry. All in all, it has been a busy month.Today the company also introduced four new IntelliFlash…

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Semiconductor Engineering Article: Wednesday At DAC 2018

Wednesday starts with a visionary talk followed by a keynote. … The keynote was given by David A. Patterson of Google and the University of California, Berkeley and looked at “A New Golden age for Computer Architecture: Domain Specific Accelerators and Open RISC-V.” He started by looking at computer architectures through history, ending up with the progression that led to the predecessors of RISC-V. Then he went through the challenges…

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