RISC-V News

ARM’s rebuttal to RISC-V: “The Case for Licensed Instruction Sets”

MICROPROCESSOR Report has publicly released an extended version of our technical report “Instruction Sets Should Be Free: The Case For RISC-V” and ARM’s corresponding rebuttal.  The RISC-V publication webpage has been updated with the following links: The Case for Open Instruction Sets, by Krste Asanovic and David Patterson, UC Berkeley The Case for Licensed Instruction Sets, by Ian Smythe and Ian Ferguson, ARM

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RISC-V just got a new logo!

As we were getting ready for HotChips, we realized we were missing something very important: A logo!

Thanks to the creative designers at 99designs, we were able to get a pretty good logo in a week. The symbol visualizes RV, which we often use to abbreviate RISC-V when naming an ISA variant. The logo comes in two layouts. First, here’s the tall RISC-V logo:

riscv-symbol-text-standard-tall-square
…more…

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RISC-V GDB port

A RISC-V port of GDB is now available at https://github.com/mythdraenor/riscv-gdb.git courtesy of Todd Snyder at Bluespec, Inc., enabling source-level debugging of C/C++ codes compiled for RISC-V.  For any questions about this, please email support@bluespec.com.

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RISC-V User-Level ISA Version 2.0 is released!

This document is also available as Technical Report UCB/EECS-2014-54. This represents the final frozen version of the base and standard extensions (IMAFD).  We are still working on the draft of the privileged ISA design, but hope to release early this summer for comments.

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ISA specification version 2.0-1e-4 now available

After extensive rework based on feedback, we have finally released version 2.0-1e-4 of the user-level ISA spec. This is a major reworking of the ISA encoding, but we have updated all of our software tools to match. We anticipate this will be the final official version of the ISA, but welcome additional comments and feedback.

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