RISC-V Ecosystem News

Inside Secure And Andes Join Forces To Deliver Secure IoT Solutions To Chipmakers For Greater China And Asia Markets

Inside Secure (Euronext Paris: INSD), at the heart of security solutions for mobile and connected devices, and Andes Technology Corporation (TWSE: 6533), a leading supplier of high performance/low-power Central Processing Unit and System-On-Chip platforms for embedded systems in Asia, are announcing a strategic partnership to bring the most advanced security capabilities to chipmakers for IoT applications and cloud connectivity. This solution combines Inside Secure’s advanced Root-of-Trust Engine with Andes Technology’s…

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All About Circuits Article: RISC-V: Opening A New Era Of Innovation For Embedded Design

In this article Ted Marena from Microsemi explores the benefits behind RISC-V’s open-source hardware model, discussing it’s longevity, portability, and reliability.The momentum behind RISC-V for embedded applications is undeniable. Today, the RISC-V Foundation has over 100 companies behind the free and open RISC-V instruction set architecture (ISA), and its membership is growing rapidly as more tools, software, hardware, and operating system vendors jump on board. With its expanding ecosystem, RISC-V gives…

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Hackday Article: SiFive Releases Smaller, Lower Power RISC-V Cores

Today, SiFive has released two new cores designed for the lower end of computing. This adds to the company’s existing portfolio of microcontrollers and SoCs based on the Open RISC-V ISA. Over the last two years, SiFive has introduced a number of cores based on the RISC-V ISA, an Open Architecture ISA that gives anyone to design and develop a microcontroller or microprocessor platform. These two new cores fill out the…

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SiFive Unveils E2 Core IP Series For Smallest, Lowest Power RISC-V Designs

SiFive, the leading provider of commercial RISC-V processor IP, today announced the availability of its E2 Core IP Series, configurable low-area, low-power microcontroller (MCU) cores designed for use in embedded devices. The E2 Series extends SiFive’s product line with two new standard cores, the E21, which provides mainstream performance for MCUs, sensor fusion, minion cores and smart IoT markets; and the E20, the most power-efficient SiFive standard core designed for…

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Embedded Computing Design Article: RISC-V Arrives

In SiFive’s pizzeria-esque vision, a customer visits a website and begins a template-driven process not unlike a standing up a virtual environment in the cloud. First, select from a basic offering of processor cores, complete with standard peripherals already onboard. Next, stop at the marketplace and grab some third-party components. Finally, top it all off with your own value-added custom IP. Toss the whole thing in the oven, and voila—a…

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Embedded Computing Design Article: Open-Source RISC-V Architecture Is Changing The Game For IoT Processors

Over the past decade, open source software has been one of the biggest catalysts in the tech world. Today, the power of open source, the freedom it enables and the communities that it generates are gaining traction in the hardware world too. For these reasons RISC-V is gaining huge popularity. Here is an introduction to RISC-V and the opportunities it opens.RISC-V is an open instruction set architecture (ISA) originally developed…

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Embedded Computing Design Article: Open Compute With RISC-V And Memory Fabrics

In the last few years, we have witnesses a massive change in how data is generated, processed, and further leveraged to garner additional value and intelligence, all influenced by the emergence of new computational models based on deep learning and neutral network applications. This profound change started in the data center where deep learn in techniques were used to offer insights into vast data volumes, mostly to classify and/or recognize…

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Andes Technology Corp. To Present At The TSMC OIP Theater During Design Automation Conference 2018 To Feature New RISC-V CPU Cores In Booth 2658

WHO:  Andes Technology Corporation, the leading Asia-based supplier of small, low-power, high performance 32/64-bit embedded CPU cores, today announced that it will present in the TSMC OIP Theater during the 2018 Design Automation Conference. The company will exhibit its latest RISC-V CPU IP cores in booth 2658.WHAT:  Andes Technology Corporation Field Application Engineer, I-Tao Tsai will present” Taking RISC-V to Mainstream ASICs.”WHEN:   Andes FAE I-Tao Tsai will present Monday June 25th from 3:15pm…

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Electronics Weekly Article: UltraSoc Links With Imperas

UltraSoC will incorporate key elements of Imperas’ development environment into its tools offering, giving designers a unified system-level pre- and post-silicon development flow, dramatically reducing time-to-revenue and overall development costs.UltraSoC delivers the industry’s leading independent on-chip monitoring, analytics and debug technology, via a combination of semiconductor IP and associated software. Imperas’ virtual platforms approach allows software developers to start work at the earliest possible stage in an SoC project.Combining the…

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UltraSoC Embedded Analytics And Imperas Virtual Platforms Combine To Enhance Multicore Development And Debug

UltraSoC and Imperas today announced a wide-ranging partnership that will provide developers of multicore systems on chip (SoCs) with a powerful combination of embedded analytics and virtual platform technologies. Under the terms of the agreement, UltraSoC will incorporate key elements of Imperas’ development environment into its tools offering, giving designers a unified system-level pre- and post-silicon development flow, dramatically reducing time-to-revenue and overall development costs.UltraSoC delivers the industry’s leading independent on-chip monitoring, analytics…

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