RISC-V Ecosystem News

China Times Article: “Semiconductor” Smart RISC-V ASIC Solution To Promote Mass Production Of AIoT SoC

ASIC design services and IP R&D and sales vendor Zhiyuan released its RISC-V-based ASIC platform solution, which has been successfully applied to the design and mass production of next-generation terminal artificial intelligence and IoT SoC. The solution includes complete system level design services such as RISC-V core IP integration, SoC design verification, and a complete peripheral driver and RTOS reference design kit. Zhiyuan has assisted major customers in mass production of RISC-V…

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Electronic Design Article: Electronic Design Products Of The Week (4/8-4/12)

Here’s Part 2 of our round-up of standout embedded and test products from the recent Embedded World 2019. Highlighted products range from an automotive network stack to a 32-Mpixel image sensor to an IoT stack for RISC-V.wolfSSL, a provider of TLS cryptography, and Hex-Five Security, developer of MultiZone Security, have partnered to bring what’s claimed as an industry-first secure IoT stack for RISC-V. The move brings a TLS 1.3 reference…

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SmartDV’s DVCon China Exhibit To Showcase Extensive Verification IP Portfolio

WHO: SmartDV™ Technologies, the Proven and Trusted choice for Verification IPWHAT: Will highlight TileLink Verification IP for RISC-V based systems and SimXL, Synthesizable Transactors for accelerating system-level SoC testing on hardware emulators and FPGA prototyping platforms at DVCon China in Booth #110. Also highlighted will be its large portfolio of Verification IP used at more than 120 leading networking, storage, wireless and memory companies, and support for all commercial simulators, emulators, formal tools and verification languages.WHEN: Wednesday, April 17WHERE: Crowne…

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SiFive Launches The World’s Smallest Commercial 64-Bit Embedded Core

SiFive, the leading provider of commercial RISC-V processor IP, today announced the launch of the S2 Core IP Series at the Linley Spring Processor Conference in Santa Clara. The S2 Core IP Series is a 64-bit addition to SiFive’s 2 Series Core IP and brings advanced features to SiFive’s smallest microcontrollers. The S2 Series further adds to SiFive’s extensive, vastly customizable, optimized, silicon-proven, embedded core IP portfolio, which comprises the…

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Electronics Weekly Article: Asic Service Offers RISC-V For IoT And AI

Taiwan asic design house Faraday Technology is offering RISC-V processor IP for chips aimed at AI and IoT.“This solution encompasses system-level design services, such as RISC-V core IP integration, SoC design verification, as well as a reference design kit consisting of RTOS and peripherals drivers,” said the firm, adding that it has already enabled mass production of RISC-V based AI SoCs on UMC’s 55ULP process. aimed at battery-powered IoT edge devices.Hardware…

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Circuit Cellar Article: RISC-V Processor Family Spans From Low-End To 64-Bit With FPU

As part of its Cortus IC Design Service offering, Cortus has announced the general availability of a complete range of RISC-V processors. These are now available for design-in in customer ASIC designs implemented by the experienced teams at Cortus. A wide range of application needs are covered by the 6 processor cores.The range starts with a low gate count, very low power 32 bit CPU core—the APS1V (RV32EMC). A more…

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Electronic Design Article: Delivering High Performance RISC-V Platforms

In this webinar, SiFive President and CEO Dr. Naveed Sherwani will introduce and explain the benefits of RISC-V and will give an overview of SiFive’s core, silicon, and ecosystem offerings. Naveed will answer detailed questions on the benefits of RISC-V implementations and SiFive’s unique cloud based design platform. Naveed will be in the hot seat regarding competitive positioning and the current state of development. To read more, please visit: https://www.electronicdesign.com/webcasts/delivering-high-performance-risc-v-platforms.

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Elektronik Article: High Demand For RISC V Cores In 2018

In 2018, Andes Technology Corporation – a provider of small, low power, high performance 32/64-bit embedded CPU cores, including a broad family of RISC V cores based in Hsinchu City, Taiwan – announced a record number of design awards for their new family of RISC V processors. These include the 32-bit N25F / A25 processors and 64-bit NX25F / AX25 processors . For Andes, the 21 license agreements mean a dramatic increase in the number of licenses signed shortly…

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NDSS Symposium Video: NDSS 2019 TIMBER-V: Tag-Isolated Memory Bringing Fine-grained Enclaves to RISC-V

At the Network and Distributed System Security (NDSS) Symposium 2019, 24-27 February 2019, Catamaran Resort Hotel & Spa in San Diego, California, Samuel Weiser, Mario Werner, Maja Malenko and Stefan Mangard at Graz University of Technology, and  Ferdinand Brasser and Ahmad-Reza Sadeghi at Technische Universität Darmstadt presented “TIMBER-V: Tag-Isolated Memory Bringing Fine-grained Enclaves to RISC-V.” They presented TIMBER-V, a new tagged memory architecture featuring flexible and efficient isolation of code and…

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