RISC-V Ecosystem News

Sohu Article: Huami’s Huangshan No. 1 Chip Started Commercial! Launched Two New Smartwatches

Huang Wang, Founder, Chairman and CEO of Huami Technology, officially announced that the artificial intelligence chip, Huangshan No. 1, has been mass-produced. He said that Huangshan No. 1 is the first artificial intelligence chip in the global smart wear field, and the world’s first wearable processor with RISC-V ISA integration. To read more, please visit: http://www.sohu.com/a/319915854_115978. Please note that the original article is in Chinese.

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Elektroniktidningen Article: The Future Of RISC-V From The Creator’s Perspective

The electronics magazine had a chat with RISC-V designer Krste Asanovi when his company SiFive passed Kista on its ongoing world tour. Krste Asanovi having produced the first version in 2010, is the perfect person to address “Linus Torvalds for RISC-V.”The RISC-V ISA was released under open source license and was intended for educational use, but has developed into a tool of a variety of applications. To read more, please visit: http://www.etn.se/index.php/nyheter/65896-framtiden-for-risc-ur-skaparens-perspektiv.html

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Imperas And Metrics Collaborate To Jump Start RISC-V Core Design Verification Using Open Source Instruction Stream Generator

Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced the collaboration with Metrics, working on the verification challenges required for RISC-V cores to achieve the required tape-out-ready quality for broad adoption by silicon designers. Imperas and Metrics will be demonstrating the early stages of this framework using the Google open source Instruction Stream Generator for RISC-V processors and Google cloud services at the RISC-V Workshop Zurich…

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Elektroniktidningen Article: New Forum For Open Hardware

The initial capital is Core-V, a new family of open-source cores in the RISC-V architecture designed for integration into system circuits.Pulp, an already existing core from ETH Zurich and the Bologna University, becomes a first member of the Core-V family.Core-V will be developed within the non-profit organization OpenHW Group which has thirteen founders: Alibaba, Bluespec, CMC, Embecosm, ETH Zurich, Greenwaves, Imperas, Metrics, Mythic AI, NXP, Onespin, Silicon Labs and Thales. Additional…

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Elektroniktidningen Article: Taiwanese Risc-V With Extras

Andes 32-bit Risc-V core N22 is available for free testing and research. It is also possible to license it in volume.The N22 is a configurable CPU with selectable support for interrupt, local memory, instruction cache, debugging and Arms open IP block bus AHB. The latter includes a number of standard peripheral cores to connect to AHB.The core is small and the pipeline is just two steps, but it delivers 3.95 Coremark…

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New Electronics Article: SiFive Attracts Strong Venture Backing Raising $65M

Leading provider of commercial RISC-V processor IP and silicon solutions, SiFive, has raised $65 million in a Series D funding round led by existing investors alongside new investor Qualcomm Ventures LLC.This Series D round brings the total investment in SiFive to more than $125 million.“SiFive continues to drive rapid RISC-V growth, development and adoption,” said Stefan Dyckerhoff, managing director at Sutter Hill Ventures and member of the SiFive board of…

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The Next Platform Article: Europe’s Homegrown HPC Compute Begins To Take Shape

At the recent EuroHPC Summit in Poland, the nature of Europe’s first homegrown HPC processor was described in some detail. The design incorporates Arm, RISC-V, high bandwidth memory, and other technologies in a multi-tile package that will be used to power Europe’s first exascale supercomputers. The work is being performed under the European Processor Initiative (EPI), an EC-funded project whose aim is to develop indigenous chip technology for HPC, AI, and other…

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Andes Technology Launches RISC-V FreeStart Program With Its Commercial-Grade CPU N22

Andes Technology Corporation, a leading supplier of high performance, low-power, compact 32/64-bit CPU cores embedded in over 1 billion SoC in 2018 alone, today announces its RISC-V FreeStart program. The program offers an easy and fast way to build a solid SoC foundation on the commercial-grade RISC-V CPU core N22, available for free download. AndesCore™ N22 is an entry-level, ultra-compact, low-power and performance-efficient RISC-V CPU IP. It delivers the highest…

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EETimes Article: Qualcomm Takes Stake in SiFive

Qualcomm Ventures is the newest investor in SiFive, the RISC-V processor IP startup. It’s a clear signal Qualcomm plans to exploit the potential of the RISC-V architecture in wireless and mobile. SiFive announced it raised $65.4 million in funding, with another $11m for its Chinese sister company SaiFan China.SiFive also said it has achieved its 101 design win. The company is claiming it has significant traction in embedded markets as device…

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HPCwire Article: Qualcomm Invests In RISC-V Startup SiFive

This week, another RISC-V startup, SiFive, announced a $65.4 million funding round that included new investor Qualcomm Ventures. SiFive, San Mateo, Calif., has so far raised more than $125 million, and is seen as a challenger to chip IP leader Arm.Observers note that wireless modem leader Qualcomm is among Arm’s biggest customers, making its investment in SiFive intriguing. Also participating in the Series D round were existing investors Chengwei Capital of…

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