RISC-V Ecosystem News

Hackaday Article: VexRISC-V Exposed

If you want to use FPGAs, you’ll almost always use an HDL like Verilog or VHDL. These are layers of abstraction just like using a C compiler for machine language or assembly code. There are other challengers such as SpinalHDL, which have small but enthusiastic followings. [Tom] has a post about how the VexRISC-V CPU leverages SpinalHDL make an extremely flexible system that is as efficient as plain Verilog. He says the…

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Cadence Blog Post: RISC-V: Real Products In Volume

I titled my preview of the RISC-V Summit RISC-V Summit Preview: Pascal or Linux? Since it is clear that RISC-V is really the only game in town inside academia, but it still hasn’t conquered the commercial world. So it’s already Pascal but not Linux.Some Highlights of the SummitIt is still too soon to say, but here are a few datapoints that I will either cover in more detail below or in future…

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AB Open Article: Tom Verbeure On The VexRiscV CPU: “A New Way To Design”

Engineer Tom Verbeure has written up an analysis of the VexRiscV CPU, a RISC-V design implemented using the novel SpinalHDL hardware description language (HDL) – an approach he describes as being “as efficient as the most optimized Verilog, yet at the same time extremely configurable.”First-prize winner in the recent RISC-V Soft-Core CPU Contest, VexRiscV eschews traditional development methodologies in favour of using the novel SpinalHDL language – a Scala library…

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Linux Press Article: RISC-V Summit Debuts To Showcase Open Source ISA

This week there’s further proof that RISC-V has arrived. Over 1,000 professionals, mostly on the hardware side of tech, attended the first ever RISC-V Summit at the Santa Clara Convention Center in Silicon Valley. To read more, please visit: http://linux.press/risc-v-summit-debuts-to-showcase-open-source-isa/.

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ExtremeTech Article: Western Digital Announces Plans For Its Own RISC-V Processor

RISC-V hasn’t been a huge topic for us at ExtremeTech, but the fully open-source CPU instruction set architecture (ISA) has been building momentum in the industry over the past few years as more companies have signed on to build RISC V-compatible processors. While it’s not the first open-source ISA, RISC-V is designed to be used in a wider range of devices than some of the previous work in this space. Now, Western…

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eeNews Embedded Article: New Core And Tools Make Implementing RISC-V Quicker

Codasip has launched the latest version of the company’s Studio tool and the Bk7 RISC-V core, which has been optimised for Linux and real-time performance. Studio allows a high-level description of a processor to be written in CodAL and then automatically synthesize the design’s RTL, test bench, virtual platform models, and processor SDK (C/C++ compiler, debugger, profiler, etc.). Development time is reduced due to the methodology that uses an Instruction…

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Embedded Computing Design Article: Western Digital Announces New “Open” Solutions, Including A RISC-V Core

Western Digital (WD) has been one of the most vocal proponents for the RISC-V instruction set architecture (ISA). The company recently took another step toward “putting its money where its mouth is” when it unveiled plans to release a new open-source RISC-V core, an open standard initiative for cache coherent memory over a network, and an open-source RISC-V instruction set simulator. This announcement was made as part of WD CTO Martin Fink’s…

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Semiconductor Engineering Article: Week In Review: Design, Low Power

RISC-V Western Digital announced big plans for RISC-V with a new open source RISC-V core, an open standard initiative for cache coherent memory over a network, and an open source RISC-V instruction set simulator. The SweRV Core features a 2-way superscalar design with a 32-bit, 9 stage pipeline core. It has clock speeds of up to 1.8Ghz on a 28mm CMOS process technology and will be used in various internal embedded designs….

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Electronics Weekly Article: A View From The RISC-V Summit

There were two announcements from IAR Systems in support of establishing a robust ecosystem for RISC-V. The first was with IP provider, SiFive, to collaborate on bringing the former’s compiler and debugger tools to the configurable processor core IP.Integration of tools and IP is expected to support developers to deliver products and to increase deployment of the open, free instruction set architecture (ISA).The software company also announced a partnership with CPU IP provider, Andes, to…

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Electronic Design Article: Hard-Core RISC-V Cores Mate With FPGA

By integrating hard-core RISC-V CPUs with its latest FPGAs, Microsemi, a Microchip company, has further bolstered its RISC-V support. This is the same approach that Intel/Altera and Xilinx have done with Arm cores and their system-on-chip (SoC) FPGA offerings. Microsemi also has an FPGA with a hard-core ARM Cortex-M3, but its Mi-V initiative has been pushing soft-core RISC-V support in its FPGA lines.Microsemi’s 64-bit RISC-V SoC FPGA is based on its PolarFire FPGA. The approach…

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