RISC-V Ecosystem News

Bluespec Unveils Groundbreaking “RISC-V Factory” — Empowering Open Source Hardware Developers To Build Faster And More Efficiently

RISC-V just got easier.Bluespec is thrilled to announce the launch of their latest innovation: the Bluespec RISC-V Factory. From developers to embedded systems engineers and beyond, those working in the RISC-V field now have a brand new resource at their fingertips that enables them to become RISC-V power users and design with RISC-V open source cores far more safely and efficiently.article: https://bluespec.com/2019/12/20/bluespec-unveils-groundbreaking-risc-v-factory-empowering-open-source-hardware-developers-to-build-faster-and-more-efficiently/

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How RISC-V Is Creating A Globally Neutral, Open Source Processor Architecture | Dean Takahashi, VentureBeat

Arm dominates the microprocessor architecture business, as its licensees have shipped 150 billion chips to date and are shipping 50 billion more in the next two years. But RISC-V is challenging that business with an open source ecosystem of its own, based on a new kind of processor architecture that was created by academics and is royalty free.article: https://venturebeat.com/2019/12/20/how-risc-v-is-creating-a-globally-neutral-open-source-processor-architecture/

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ONiO.zero Offers Up To 24MHz Of RISC-V Microcontroller Performance On Nothing But Harvested Energy | Gareth Halfacree, Hackster.io

Norwegian healthcare-focused Internet of Things (IoT) specialist ONiO has unveiled ONiO.zero, an ultra-low-power RISC-V-based microcontroller capable of operating wholly from harvested energy — without needing a battery, capacitor, or any other form of energy storage.article: https://www.hackster.io/news/onio-zero-offers-up-to-24mhz-of-risc-v-microcontroller-performance-on-nothing-but-harvested-energy-70285321d50d

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Microchip Unveils Details And Opens Early Access Program For RISC-V Enabled Low-Power PolarFire SoC Family | Intelligent Aerospace

CHANDLER, Ariz., – The trend towards compute intensive gateways and edge devices is driving the integration of traditional deterministic control applications with additional embedded processing capabilities needed for smart and secure connected systems. In response, Microchip Technology Inc. in Chandler, Ariz., is opening the early access program (EAP) for the PolarFire field programmable gate array (FPGA) system-on-chip (SoC). The platform offers hardened real-time, Linux capable, RISC-V-based microprocessor subsystem on the award-winning, mid-range PolarFire FPGA family,…

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Will Open-Source Processors Cause A Verification Shift? | Ann Steffora Mutschler, Semiconductor Engineering

While the promised flexibility of open source could have advantages and possibilities for processors and SoCs, where does the industry stand on verification approaches and methodologies from here? Single-source ISAs of the past relied on general industry verification technologies and methodologies, but open-source ISA-based processor users and adopters will need to review the verification flows of the processor and SoC.article: https://semiengineering.com/will-open-source-processors-cause-a-verification-shift/

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Ultra-Low Power AI Chip Ups The Ante | Sally Ward-Foxton, EE Times

LONDON – The next generation of GreenWaves’ ultra-low power AI accelerator, GAP9, will use five times less power than its predecessor, GAP8, while handling algorithms that are 10x bigger. The new device will offer up to 50 GOPS at an overall power consumption of 50mW. This is down to a combination of architectural improvements and a new state-of-the-art FD-SOI (fully depleted silicon on insulator) process technology.article: https://www.eetimes.com/ultra-low-power-ai-chip-ups-the-ante/

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What’s Happening in RISC-V Land? | Paul McLellan, Cadence

Last week was IEDM, the International Electronic Devices Meeting. I will write about that later this week, because last week was also the RISC-V Summit, which was originally scheduled for the week before in the Santa Clara Convention Center, but got pushed out a week and moved to the San Jose Convention Center. IEDM is in San Francisco, so I mostly attended IEDM but I came down to San Jose…

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AndesCore 27-Series Linux RISC-V SoC Features A Vector Processing Unit | Stephen Vicinanza, CNX Software

Andes has developed a Linux capable RISC-V based SoC which runs on the first Vector Processing Unit (VPU) that is reported to be groundbreaking in its application ability, especially in the AI sector. The Andes 27 Series CPU has debuted in the RISC-V Summit in San Jose, to a great deal of talk in many quarters.article: https://www.cnx-software.com/2019/12/13/andescore-27-series-linux-risc-v-soc-features-a-vector-processing-unit/

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Samsung To Use SiFive RISC-V Cores For SoCs, Automotive, 5G Applications | Anton Shilov, AnandTech

At the annual RISC-V Summit this week, Samsung disclosed the use SiFive’s RISC-V cores for upcoming chips for a variety of applications. The company is joining a growing list of leading high-tech companies that have adopted the RISC-V architecture.One of the applications that Samsung is using RISC-V cores in is mmWave RF processing by its upcoming 5G RF front-end modules. The latter will be used for Samsung’s flagship 5G smartphones due in 2020….

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