RISC-V Ecosystem News

Will Open-Source Processors Cause A Verification Shift? | Ann Steffora Mutschler, Semiconductor Engineering

While the promised flexibility of open source could have advantages and possibilities for processors and SoCs, where does the industry stand on verification approaches and methodologies from here? Single-source ISAs of the past relied on general industry verification technologies and methodologies, but open-source ISA-based processor users and adopters will need to review the verification flows of the processor and SoC.article: https://semiengineering.com/will-open-source-processors-cause-a-verification-shift/

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Ultra-Low Power AI Chip Ups The Ante | Sally Ward-Foxton, EE Times

LONDON – The next generation of GreenWaves’ ultra-low power AI accelerator, GAP9, will use five times less power than its predecessor, GAP8, while handling algorithms that are 10x bigger. The new device will offer up to 50 GOPS at an overall power consumption of 50mW. This is down to a combination of architectural improvements and a new state-of-the-art FD-SOI (fully depleted silicon on insulator) process technology.article: https://www.eetimes.com/ultra-low-power-ai-chip-ups-the-ante/

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What’s Happening in RISC-V Land? | Paul McLellan, Cadence

Last week was IEDM, the International Electronic Devices Meeting. I will write about that later this week, because last week was also the RISC-V Summit, which was originally scheduled for the week before in the Santa Clara Convention Center, but got pushed out a week and moved to the San Jose Convention Center. IEDM is in San Francisco, so I mostly attended IEDM but I came down to San Jose…

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AndesCore 27-Series Linux RISC-V SoC Features A Vector Processing Unit | Stephen Vicinanza, CNX Software

Andes has developed a Linux capable RISC-V based SoC which runs on the first Vector Processing Unit (VPU) that is reported to be groundbreaking in its application ability, especially in the AI sector. The Andes 27 Series CPU has debuted in the RISC-V Summit in San Jose, to a great deal of talk in many quarters.article: https://www.cnx-software.com/2019/12/13/andescore-27-series-linux-risc-v-soc-features-a-vector-processing-unit/

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Samsung To Use SiFive RISC-V Cores For SoCs, Automotive, 5G Applications | Anton Shilov, AnandTech

At the annual RISC-V Summit this week, Samsung disclosed the use SiFive’s RISC-V cores for upcoming chips for a variety of applications. The company is joining a growing list of leading high-tech companies that have adopted the RISC-V architecture.One of the applications that Samsung is using RISC-V cores in is mmWave RF processing by its upcoming 5G RF front-end modules. The latter will be used for Samsung’s flagship 5G smartphones due in 2020….

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Veridify Security To Demonstrate DOME A Zero-Touch Onboarding And Device Management Solution For RISC-V Processors | Tiera Oliver, Embedded Computing Design

Veridify Security, formerly SecureRF, develops and licenses quantum-resistant, public-key security tools for the low-resource processors powering the Internet of Things (IoT), announced they will demonstrate DOME, a zero-touch onboarding and ownership management platform for RISC-V processors, at the RISC-V Summit, Dec. 10-12 at the San Jose Convention Center.article: https://www.embedded-computing.com/hardware/veridify-security-to-demonstrate-dome-a-zero-touch-onboarding-and-device-management-solution-for-risc-v-processors

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Linux-Driven RISC-V Core To Debut On An NXP i.MX SoC | Eric Brown, LinuxGizmos

The OpenHW Group unveiled a Linux-driven “CORE-V Chassis” eval SoC due for tape-out in 2H 2020 based on an NXP i.MX SoC, but featuring its RISC-V and PULP-based 64-bit, 1.5GHz CV64A CPU and 32-bit CV32E cores. Meanwhile, Think Silicon demonstrated a RISC-V based NEOX|V GPU.article: http://linuxgizmos.com/linux-driven-risc-v-core-to-debut-on-an-nxp-i-mx-soc/

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