RISC-V Ecosystem News

OneSpin Joins The RISC-V Foundation

OneSpin® Solutions today joined the RISC-V Foundation, a non-profit corporation controlled by its members to drive a new era of processor innovation via the adoption and implementation of the free and open RISC-V instruction set architecture (ISA).This follows an earlier announcement that OneSpin, provider of certified IC integrity verification solutions for building functionally correct, safe, secure and trusted integrated circuits, released its RISC-V Integrity Verification Solution. The solution enables the…

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Cycle-Accurate Trace Boosts Performance Optimization Capabilities Of UltraSoC Embedded Analytics Infrastructure

UltraSoC today announced new technology within its embedded monitoring and analytics infrastructure that allows designers of high-performance computing, storage and real-time devices to squeeze ultimate levels of performance from their products. The addition of cycle-accurate trace enables developers of real-time applications using UltraSoC’s embedded analytics to see not only what is happening inside devices, but critically, when something occurred.Cycle-accurate tracing is increasingly important in real-time and performance-critical applications, where engineers…

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Evertiq Article: SiFive Expands Into Portland Area’s Silicon Forest

SiFive has opened a development office in Beaverton, Oregon, to provide local support to customers and partners and help fuel the mass adoption of the RISC-V Instruction Set Architecture (ISA) taking place in the region and throughout the world.The Beaverton office will be managed by Sunil Shenoy, senior vice president and general manager of the RISC-V Business Unit at SiFive. The company’s current development tools team, established in September 2018…

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Fudzilla Article: Boffins Claim To Have Invented Unhackable Chip

University of Michigan boffins have developed what they claim is an ‘unhackable’ self-encrypting processor based on the RISC-V instruction set architecture (ISA).According to Bit-Tech, researchers at the University of Michigan have opted to concentrate on security on the open RISC-V and create an ‘unhackable’ processor.The build something called Morpheus which sees code and data internally encrypted and shuffled 20 times a second which is ‘infinitely faster than a human hacker…

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CNX Software Article: Linux 5.1 Release – Main Changes, Arm, MIPS And RISC-V Architectures

Linux 5.0 release brought us Adiantum file system encryption for fscrypt, support for AMDGPU FreeSync, Btrfs swap file support, Energy-aware Scheduling for Arm big.LITTLE, and many other changes. It was also the first release where I started to cover RISC-V changelog.RISC-V updates for Linux 5.1: A handful of cleanups to our kernel prints, most of which are things I should have caught the first time. We now provide an HWCAP…

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Hackster.io Article: Now On GroupGets: RISC-V LoFive R1

The RISC-V LoFive breakout just received a fresh update and here to tell you about it in his own words is Michael Welling of Qwerty Embedded Design. Welling is no stranger to using GroupGets to crowdfund production funds for his works. He graciously brought us the PocketBone, the original LoFive, and BaconBits. While on his flight home from the first KiCon in Chicago, our co-founder Ron Justin shot him over…

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Codasip Presence At Upcoming Events: China Roadshow, DAC 2019, And RISC-V Workshop Zurich

Codasip GmbH, the leading supplier of configurable RISC-V® embedded processor IP, is going to be featured at three major industry events around the globe in the second quarter of 2019: China Roadshow 2019, Design Automation Conference in Las Vegas, and RISC-V Workshop in Zurich.“Getting Started with RISC-V” Roadshow 2019, May 6–16, is a series of events taking place in five cities across China in eleven days. The show aims to present…

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Bit-tech Article: Researchers Unveil ‘Unhackable’ Morpheus Processor

Researchers at the University of Michigan have developed what they claim is an ‘unhackable’ self-encrypting processor based on the RISC-V instruction set architecture (ISA).The open nature of the RISC-V instruction set architecture (ISA), one of a growing number of free and open source silicon (FOSSi) ISAs designed to bring competition to proprietary architectures like x86 and Arm, makes it well-suited to use in research projects. Most of these projects concentrate…

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Tech Xplore Article: New Chip Stops Attacks Before They Start

A new computer processor architecture developed at the University of Michigan could usher in a future where computers proactively defend against threats, rendering the current electronic security model of bugs and patches obsolete.Called MORPHEUS, the chip blocks potential attacks by encrypting and randomly reshuffling key bits of its own code and data 20 times per second—infinitely faster than a human hacker can work and thousands of times faster than even…

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SiFive Expands Into Silicon Forest With New Development Office In Beaverton, Oregon

SiFive, the leading provider of commercial RISC-V processor IP and custom SoC solutions, today announced it is expanding into the metropolitan Portland area with the opening of a development office in Beaverton, Oregon. The primary mission of the office is to provide local support to existing SiFive customers and partners as well as to help fuel the mass adoption of the RISC-V Instruction Set Architecture (ISA) that is taking place…

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