RISC-V Ecosystem News

Driving To Data-Centric Architectures And 1B RISC-V Cores | Office of the CTO, Western Digital

Two years ago we kicked off our commitment to open-source innovation by announcing our goal to transition over one billion cores per year to RISC-V. As a founding member of the 150+ organization-strong RISC-V Foundation, our commitment hasn’t wavered and we’re proving it at the RISC-V Summit 2019. From new announcements about technical innovations to keynotes including Martin Fink’s Unshackling Memory, which discussed how today’s compute platforms have evolved and how RISC-V is…

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RISC-V Based PolarFire SoC FPGA And Devkit Coming In Q3 2020 | Jean-Luc Aufranc, CNX Software

Microsemi unveiled PolarFire FPGA + RISC-V SoC about one year ago, but at the time, development was done on a $3,000 platform with SiFive U54 powered HiFive Unleashed board combined with an FPGA add-on board from Microsemi.I’ve now been informed that Microchip has announced its Linux-capable PolarFire FPGA+RISC-V SoC would start shipping in Q3 2020 at the RISC-V summit and that a development kit will be sold for a few hundred dollars.article: https://www.cnx-software.com/2019/12/11/risc-v-based-polarfire-soc-fpga-and-devkit/

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RISC-V Grows Globally As An Alternative To Arm And Its License Fees | Dean Takahashi, VentureBeat

ARM is the most successful microprocessor architecture on the planet, with its licensees shipping billions of chips a year. But a rival has emerged in the past few years called RISC-V, a new kind of royalty-free architecture started by academics. Its proponents are holding an event in the heart of Silicon Valley to tout its growth.article: https://venturebeat.com/2019/12/11/risc-v-grows-globally-as-an-alternative-to-arm-and-its-license-fees/

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Microchip Announces First RISC-V-Based SoC FPGA To Use Half The Power Of Other FPGAs | Lisa Boneta, All About Circuits

Microchip’s new RISC-V-based PolarFire SoC family is said to provide 50% lower power than competing mid-range FPGAs. Microchip recently announced the Early Access Program (EAP) for their low-power, RISC-V-enabled PolarFire SoC family, based on their award-winning PolarFire FPGA family. The PolarFire SoC family is the world’s first SoC FPGA with a RISC-V-based microprocessor subsystem. article: https://www.allaboutcircuits.com/news/microchip-announces-first-risc-v-based-soc-fpga-to-use-half-the-power-of-other-fpgas/

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SiFive Learn Inventor Is A Wireless RISC-V Development Kit Inspired By BBC Micro:bit | Jean-Luc Aufranc, CNX Software

SiFive Learn Inventor is a RISC-V educational board partially inspired by BBC Micro:bit board with the same crocodile clip-friendly edge connector, and an LED matrix. The board is also fully qualified to work with the Amazon FreeRTOS real-time operating system.Shaped in the form of a hand, the board features SiFive FE310 RISC-V processor found in the SiFive HiFive1 board, as well as ESP-WROOM-32 WiFi + Bluetooth module. article: https://www.cnx-software.com/2019/12/10/sifive-learn-inventor-wireless-risc-v-development-kit-bbc-microbit/

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Codasip Partners With Western Digital On Open‑Source Processors | Julien Happich, eeNews Europe

A supplier of configurable RISC-V embedded processor IP, Codasip GmbH announced it has joined forces with Western Digital Corp. to become the preferred provider of hardware implementation packages and expert technical support for users of Western Digital’s SweRV Core EH1, a RISC-V core currently available to the open-source community and further supported by the open-source development organization CHIPS Alliance. article: https://www.eenewseurope.com/news/codasip-partners-western-digital-open-source-processors

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Andes’ Core Has RISC-V Vector Instruction Extension | Nitin Dahad, EE Times

Andes’ new processor cores enable scalability by delivering RVV instruction extension and new memory subsystem. The company claims to be the first to deliver a core with the extension to a customer.Andes Technology has released the AndesCore 27-series CPU cores, which it claims are the first licensable RISC-V core to deliver to a production licensee the RISC-V vector instruction extension (RVV). It has also re-architected the memory subsystem to sustain…

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Aerendir Mobile Inc. And SiFive Inc. Collaborate To Accelerate The Adoption Of AI-Enabled Processors | Tiera Oliver, Embedded Computing Design

Aerendir Mobile Inc., a developer of an AI-powered authentication, identification, encryption and bot segregation platform, will merge its mathematical deep learning cores and AI infrastructure with SiFive Inc., a provider of market-ready processor core IP and silicon solutions, RISC-V Core IP to enable a board format for deep learning. This combined approach will decrease the cost of true AI, allowing it to be enabled at the IoT Edge and End Point…

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