RISC-V Cores

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https://github.com/riscv/riscv-wiki/wiki/RISC-V-Cores-and-SoCs

RISC-V Cores and SoC Overview

This document captures the status of various cores and SoCs that endeavor to implement the RISC-V specification. Note that none of these cores/SoCs have passed the in-development RISC-V compliance suite.

Please add to the list and fix inaccuracies.

Cores

Rocket

ORCA

PULPino

OPenV/mriscv

VexRiscv

Roa Logic RV12

SCR1

SoCs

Rocket Chip

LowRISC

Briey

Emulators and Simulators

TODO: Flesh out these entries