Introduction to RISC-V (LFD110x)

Learn all about RISC-V: find out how to work with open specifications and the organization that curates them, and discover how you can become a part of this vibrant community.

This course is divided into five chapters:

• Chapter 1: Getting to Know RISC-V, which introduces RISC-V as a technology, an organization, and a community to give you a better understanding of what RISC-V is.
• Chapter 2: The RISC-V Story, which goes into great detail about the history of RISC-V, RISC-V International, the organization of RISC-V governance, working groups and committees, and how all of these people communicate effectively together.
• Chapter 3: The RISC-V Community, which outlines the processes by which the RISC-V community manages, extends, and improves all of the artifacts within RISC-V – the ISA and other specifications, working policies, development practices, and more.
• Chapter 4: Developing RISC-V, which uses all of the prior information to describe the hard details about collaboratively developing the specifications, software, compliance tests, and other related artifacts.
• Chapter 5: RISC-V in Practice, the hands-on chapter where you will see the RISC-V ISA in action through the use of the QEMU emulator/virtualizer, creating a processor using SystemVerilog, and running an operating system on actual hardware.

We expect that by the end of this course, you will have a solid grounding in all of the activities related to RISC-V. You will learn how to read and understand the specifications, and understand the processes involved in curating and extending them. You will understand how to work effectively with RISC-V International and the RISC-V community. And you will understand where to go for additional information.

Building a RISC-V CPU Core (LFD111x)

Create a RISC-V CPU with modern open source circuit design tools, methodologies, and microarchitecture, all from your browser.

This mini-workshop is a crash course in digital logic design and basic CPU microarchitecture. Using the Makerchip online integrated development environment (IDE), you will implement everything from logic gates to a simple, but complete, RISC-V CPU core. You will be amazed by what you can do using freely-available online tools for open-source development. You will walk away with fundamental skills for a career in logic design, and you will position yourself on the forefront by learning to use the emerging Transaction-Level Verilog language extension (even if you don’t already know Verilog).

RISC-V Toolchain and Compiler Optimization Techniques (LFD113x)

Develop a working knowledge of the internals of compiler toolchains and compiler optimization techniques with a focus on RISC-V applications.

As RISC-V has made it easier to bring up processor chipsets, the need for compiler engineers in the RISC-V ecosystem has increased. There is an implicit need for toolchain experts who can help RISC-V vendors gain an edge over competitors with their expertise in compilation technologies. Learning about internals of the toolchain, building and debugging RISC-V applications will allow you to work with thousands of companies that are building the latest hardware technologies.

Developing Embedded Linux Device Drivers (LFD435)

Embedded Linux Development (LFD450)

Embedded Linux Platform Development with Yocto Project (LFD460)

RVfpga: Complete Courses in Computer Architecture & SoC Design

RVfpga has been created to provide the foundation knowledge and hands-on experience that the next generation of Programmers and Engineers need to harness the potential of RISC-V. It is structured for Teachers to use with their Students, but can also be used for self-study. Supporting videos, workshops and online courses are available now and in further development. It is suitable for under-graduate students, and is also useful to post-grads for self-study, as well as industry professionals who want to update their skills. It’s rigorous, providing everything a Teacher needs: how to set-up the course, the hardware and software tools, lecture slides, student manuals and supplementary materials. Even suggested exam questions!
In total these materials would typical fit into three semesters, making RVfpga by far the most complete set of materials on these topics. Furthermore, they are available in seven languages: English, Simplified Chinese, Traditional Chinese, Japanese, Korean, Spanish & Turkish.

BY ACADEMICS FOR ACADEMICS
We follow the essential principle ‘by academics for academics’ in the creation of all teaching materials. RVfpga is a collaborative effort between Imagination Technologies’ University Programme (“IUP”), UNLV – University of Nevada Las Vegas and UCM – University Complutense University of Madrid. Our curriculum guides and reviewers are from UCB – University of California, Berkeley, PDX – Portland State University, and ZJU – Zhejiang University.
The RVfpga package consists of 20 Labs in total with detailed instructions, examples, short questions and practical exercises with solutions, giving teachers flexibility to choose between a practical and an exam-based structure for the course.
The materials are provided in both .pdf and .pptx/.docx formats enabling customisation by Teachers to suit their needs.

“RVfpga: Understanding Computer Architecture” instructions, tools, and labs show how to:

• Target a commercial RISC-V system to an FPGA and a Simulator
• Program the core using C and RISC-V assembly languages
• Use the peripherals from the RVfpga System and add new peripherals
• Analyse and modify the RISC-V core and memory hierarchy
• A total of two semesters of materials at typical teaching pace

“RVfpga-SoC: An Introduction to SoC Design” enables users to gain hands-on experience, understand, and walk through the process of building a System-on-Chip. RVfpga-SoC guides users through the interconnect options and adding peripherals.
It then shows how to run a real-time operating system (“RTOS”) and run a program using Tensorflow Lite on the SweRVolf core.

The RVfpga system uses Chips Alliance’s SweRVolf SoC, based on Western Digital’s RISC-V SweRV EH1 core. The SweRV is a fully-verified production level processor core. It is fully open-source, and is now being used by several companies in silicon, including by Western Digital in data storage and Imagination Technologies in their latest GPUs (A, B and C series).
SweRV is at the centre of a vibrant expanding ecosystem with many useful open-source and commercial tools available, including Simulators, Models, Integrated Development Environments, Virtual Hardware and pre-configured FPGA-ready SoC implementations. We believe passionately in sharing real-world in-silicon solutions with Students. Why use a “simplified education core” when you can use industrially proven designs?

GETTING THE MATERIALS
They are completely free-of-charge for academic and training use.

Register for the “IUP” – Imagination University Programme: https://university.imgtec.com/register

Request the materials: https://university.imgtec.com/teaching-download/

Learn more!

And2RISCV   RISC-V Online Tutor Course

• • Design-to-prototype steps for each component in a 32-bit RISC-V processor
  • Use of industry-standard AMD Xilinx Electronic Design Automation (EDA) tools and HDL modelling
  • Assembly programming of a remote RISC-V processor, using the vicilogic online assembler
  • Instruction-specific RISC-V hardware operation, with control and probing of RISC-V signal states

Maven Silicon: RISC-V Online Courses

Maven Silicon offers five on-demand online courses by Sivakumar P R.

• RISC-V Instruction Set Architecture: This RISC-V ISA course explains RISC-V Instruction Set Architecture and all RV 32 I Instructions in detail with various examples.
• RISC-V R32I RTL Design: This RISC-V RTL Design course explains the complete RTL design process, how you can create a basic architecture for J-type instructions initially and scale up the same sequentially in phases to implement all other RV 32 I instructions.
• RISC-V ISA & RV32I RTL Architecture Design: This RISC-V training course trains you extensively on the RTL design using Digital Electronics which includes the concepts of combinational, sequential, FSM logic designs and Memories.
• RISC-V RV32I RTL Design using Verilog HDL: This RISC-V hands-on training course explains the RISC-V ISA, pipeline RISC-V processor RTL design architecture and how to implement the RTL design using Verilog HDL.
• RISC-V RV32I RTL Verification using UVM: This RISC-V hands-on training course explains the RISC-V ISA, pipeline RISC-V processor RTL design architecture and how to verify the RISC-V Verilog RTL design using UVM.

Click here for Maven Silicon RISC-V Course Demo Videos.

Nuclei RISC-V Embedded Program

The RISC-V embedded program provides the foundation knowledge of RISC-V  ISA, general features of Neclei’s software and hardware, and how to conduct a  complete a embedded program. 

Syllabus
This course is divided into three chapters: 

• Chapter 1: Getting to Know RISC-V, which introduces RISC-V as a  technology, to give you a better understanding of what RISC-V is; and  some details about GD32VF103 RISC-V MCU; 
• Chapter 2: introducing the Nuclei software and hardware platform, and more information about the RV-STAR board, which contains the GD32VF103;
• Chapter 3: conduct a complete RISC-V embedded program. 

Certificate
The students who finishes all the courses will receive and CEO-signed certificate  with Nuclei’s logo to verify the achievement and enlarge the job opportunities. 

Length:
4 weeks

Effort:
3-4 hours per week 

Institution:
Nuclei System Co, Ltd. 

Instructor
Hu Can, Nuclei’s RISC-V ecosystem manager. 

We expect that by the end of this course, you will have a general understanding  about RISC-V. You will learn how to conduct a started RISC-V embedded  program. This program uses the RV-STAR board, which uses the Giga Device MCU GD32VF103. This MCU based on Nuclei’s RISC-V Bubblebee core. The Bubblebee core is a fully-verified production level processor core, now being  used in silicon by several companies.

VSD-RISCV: Instruction Set Architecture (ISA), via Udemy

Part 1a: This course will talk a lot about RISC-V ISA from scratch, also including a section about why do we even need a computer architecture and how real-time day-to-day apps run on a computer, with examples

The final aim of this course is to help everyone to build a robust specifications, which is the very first criteria behind system design. In the upcoming courses,, these specifications will be coded in RTL hardware description language using verilog/vhdl and finally the RTL will placed and routed using opensource EDA tool chain.

This course will walk you through the specifications, starting from signed/unsigned integer representation till RV64IMFD Instruction set with some really cool images and examples. The conventions like “IMFD” will also be explored in a unique fashion, which is being never done before and any micro-processor or micro-controller related courses

Part 1b: This course is in continuation with my previous course, which dealt with RV64I integer instructions. We also looked at a sample program coded in RISC-V assembly language and viewed the contents of all 32 registers present in RISC-V architecture.

All concepts viewed in Part 1a form the basis of this course and viewer is expected to cover Part 1a course at least 70%. This course deals with some advanced topics of multiply extension (RV64M) and floating point extension (RV64FD) of the RISC-V architecture – An important one needed in today’s fast changing computing world.

We also have explored some facts about hardware, which is the basis of next course (to be launched soon) where we will code the RISC-V ISA using verilog.

More information:

• Part 1a (Udemy)
• Part 1b (Udemy)