Hands-On RISC-V Tutorial

register early to guarantee your attendance. The tutorials listed below have all been developed to run on the Arrow Microsemi SmartFusion2+ eval board which will be provided to all registered attendees of the Tutorial session. Yes, you get to keep the eval board!! Each Tutorial is 60 minutes in length plus an additional 10min Q&A / change over period between tutorials.  Thank you to our Tutorial Sponsors for supporting this event.       

  Tutorial attendees should bring a laptop to the tutorial session pre-configured as follows:

1. VirtualBox Client installed and running on your machine (a VM image will be supplied to attendees ahead of the tutorial session);
2. A free USB port on your machine; and
3. Basic C knowledge and familiarity FPGA / HDL concepts are required to work through the examples in this tutorial session.

1:00pm Tutorial 1 Title: Arrow Microsemi SmartFusion2+ Eval Board Bring-Up Instructor: Cyril Jean, Microsemi Description: this is a simple tutorial to help users bring-up the eval board and associated tools using the supplied VirtualBox VM.  This basic capability will be required when participating in tutorials 2, 3 and 4 below.  In this tutorial, users will:

• boot the provided VirtualBox VM
• launch the Microsemi tools
• generate a simple design using the GUI tools (RISC-V soft core, busses, memory and GPIO from the tool’s IP catalog, connect it all together)
• generate a bitstream and program it to the board using a USB cable

Prerequisites: VirtualBox Client installed and running on your machine 2:10pm Tutorial 2 Title: VectorBlox ORCA RISC V Processor with Vector Extensions Instructor: Guy Lemieux, VectorBlox Description: In this tutorial, users will:

• generate an ORCA RISC V computer system using Microsemi’s Libero FPGA design tools
• boot the processor on the Microsemi hardware
• write, compile and execute a simple audio processing application using the 2 on-board microphones
• accelerate the audio processing using the vector extensions
• accelerate more general applications by discovering the full vector instruction set

3:20pm 20-minute Break 3:40pm Tutorial 3 Title: How RISC-V Can Make Your Products Safer and More Secure Instructor: Jonathan Hofman, Technolution Description: Is your embedded product connected to the internet? Have you ever wondered how a vulnerability in your product may be exploited? Do you want to make your embedded devices or mixed criticality systems safer and more secure? This session provides a simple tutorial on hacking and adding counter measures to a device. During this tutorial session we will hack a connected application and demonstrate how using RISC-V in an FPGA can help to improve the safety and security of the connected device. The tutorial will also demonstrate FreeRTOS, the popular embedded OS which has recently been ported to RISC-V based processors. Prerequisites: During the tutorial basic Python knowledge would be helpful as it is used to communicate with the development board. 4:50pm Tutorial 4 Title: RISC-V in Chisel on FPGA Instructor: Jonathan Bachrach, EECS @ UC berkeley Description: This tutorial will teach the design of RISC-V soft-core slaves in Chisel. Specifically, attendees will implement a PWM slave attached to an LED.  They will be given a system template consisting of a RISC-V Rocket soft core and an example simple digital IO slave attached to a button and an LED along with C code to have the button drive the LED.  From there users will write a PWM slave based off the digital IO example and modify their code to drive the LED with 8 bit grey values. Attendees will learn the basics of RISC-V soft-cores and slaves along with necessary Chisel and C code to design and exploit them.  Users will be given templates and build scripts so that they will focus on the specific task at hand. Prerequisites: It would be helpful if attendees have worked through the Chisel “getting started” guide before-hand which is available at: chisel.eecs.berkeley.edu 6:00pm Tutorial Session Ends]]>