RISC-V (pronounced "risk-five") is a new instruction set architecture (ISA) designed to support computer architecture research and education. RISC-V was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley. Our goals in defining RISC-V include:

  • A completely open ISA that is freely available to academia and industry.
  • A realistic ISA that captures important details of commercial general-purpose ISA designs and is suitable for direct hardware implementation.
  • A small but complete base ISA that avoids "over-architecting" for a particular microarchitecture style (e.g., microcoded, in-order, decoupled, out-of-order) or implementation technology (e.g., full-custom, ASIC, FPGA), but which allows efficient implementation in any of these.
  • Optional variable-length instructions to both expand available instruction encoding space and to support an optional dense instruction encoding for improved performance, energy efficiency, and static code size.
  • Both 32-bit and 64-bit address space variants for applications, operating system kernels, and hardware implementations.
  • Support the revised 2008 IEEE-754 floating-point standard.
  • Simple to subset for educational purposes and to reduce complexity of bringing up new implementations.
  • Easy to extend with user-level ISA extensions and specialized variants.
  • Easy to experiment with new supervisor-level ISA designs.
  • Fully virtualizable to ease hypervisor development.
  • Support highly-parallel multicore or manycore implementations, including heterogeneous multiprocessors.

What's Available?

Right now, you can download the close-to-final user-level ISA specification, a draft of a supervisor ISA specification, and RISC-V software tools including a GNU/GCC software tool chain, an LLVM compiler, an ISA simulator, and a verification suite.

The Sodor repository of educational RISC-V cores, written in Chisel is also available. The cores include a microcoded processor, an unpipelined processor, and 2, 3, and 5-stage pipelines.

To sample the architecture without installing anything, try out ANGEL, a JavaScript ISA simulator that boots an interactive session of riscv-linux on a simulated RISC-V machine in your browser. The source code is available at riscv-angel.

Our intent is to provide a long-lived open ISA with significant infrastructure support, including documentation, compiler tool chains, operating system ports, reference software simulators, cycle-accurate FPGA emulators, high-performance FPGA computers, efficient ASIC implementations of various target platform designs, configurable processor generators, architecture test suites, and teaching materials. Initial versions of all of these have been developed or are under active development. This material is to be made available under open-source licenses.

Getting Started

Download RISC-V software tools from our riscv-tools Github repository. This top-level repository includes the following components:
  • riscv-gcc, a RISC-V GCC cross-compiler
  • riscv-llvm, a RISC-V LLVM cross-compiler
  • riscv-isa-sim, the ISA simulator and "golden standard" of execution
  • riscv-pk, a proxy kernel that services system calls generated by code built and linked with the RISC-V newlib port
  • riscv-fesvr, a "front-end" server that services calls between the host and target processors on the Host-Target Interface (HTIF)
  • riscv-tests, a set of assembly tests and benchmarks
  • riscv-opcodes, the enumeration of all RISC-V opcodes

Follow the RISC-V Toolchain Installation Manual for detailed instructions on how to build RISC-V software tools based on the RISC-V GCC/Newlib toolchain.

For those who want the Linux based RISC-V GCC/glibc toolchain and/or the full RISC-V Linux experience, follow the Linux/RISC-V Installation Manual for detailed instructions.

Funding

RISC-V has been developed as part of a number of sponsored research projects. We thank the following research sponsors for their support.

ASPIRE Lab: Research partially funded by:

Par Lab: Research supported by Microsoft (Award #024263) and Intel (Award #024894) funding and by matching funding by U.C. Discovery (Award #DIG07-10227). Additional support from Par Lab affiliates Nokia, NVIDIA, Oracle, and Samsung.

BWRC: Partially funded by DoE Award DE-SC0003624 (Project Isis).

The content of this website does not necessarily reflect the position or the policy of the US government and no official endorsement should be inferred.

RISC-V News


March 6, 2014: RISC-V LLVM is released at riscv-llvm.


March 5, 2014: Try out RISC-V Linux on ANGEL, our in-browser JavaScript ISA simulator.


January 18, 2014: After extensive rework based on feedback, we have finally released version 2.0-1e-4 of the user-level ISA spec. This is a major reworking of the ISA encoding, but we have updated all of our software tools to match. We anticipate this will be the final official version of the ISA, but welcome additional comments and feedback.


January 8, 2014: We have completed an LLVM backend for RISC-V that will be made available shortly.


August 26, 2013: Thanks to extensive feedback, we have been busy reworking the ISA spec, though this is taking longer than anticipated, so stay tuned for the next revision.


August 26, 2013: RISC-V poster at HotChips conference!


August 2, 2013: New draft ISA specification version 1.999 available. ISA will be frozen on August 16, so please send comments before then.


July 26, 2013: Draft website is up to public! Please provide feedback on the draft ISA specifications before the upcoming ISA freeze.