RISC-V (pronounced "risk-five") is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education, but which we now hope will become a standard open architecture for industry implementations. RISC-V was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley. Our goals in defining RISC-V include:

  • A completely open ISA that is freely available to academia and industry.
  • A real ISA suitable for direct native hardware implementation, not just simulation or binary translation.
  • An ISA that avoids "over-architecting" for a particular microarchitecture style (e.g., microcoded, in-order, decoupled, out-of-order) or implementation technology (e.g., full-custom, ASIC, FPGA), but which allows efficient implementation in any of these.
  • An ISA separated into a small base integer ISA, usable by itself as a base for customized accelerators or for educational purposes, and optional standard extensions, to support general-purpose software development.
  • Support for the revised 2008 IEEE-754 floating-point standard.
  • An ISA supporting extensive user-level ISA extensions and specialized variants.
  • Both 32-bit and 64-bit address space variants for applications, operating system kernels, and hardware implementations.
  • An ISA with support for highly-parallel multicore or manycore implementations, including heterogeneous multiprocessors.
  • Optional variable-length instructions to both expand available instruction encoding space and to support an optional dense instruction encoding for improved performance, static code size, and energy efficiency.
  • A fully virtualizable ISA to ease hypervisor development.
  • An ISA that simplifies experiments with new supervisor-level and hypervisor-level ISA designs.

What's Available?

Right now, you can download the final user-level ISA specification, and RISC-V software tools including a GNU/GCC software tool chain, GNU/GDB debugger, an LLVM compiler, an ISA simulator, and a verification suite.

The Sodor repository of educational RISC-V cores, written in Chisel is also available. The cores include a microcoded processor, an unpipelined processor, and 2, 3, and 5-stage pipelines.

To sample the architecture without installing anything, try out ANGEL, a JavaScript ISA simulator that boots an interactive session of riscv-linux on a simulated RISC-V machine in your browser. The source code is available at riscv-angel.

Our intent is to provide a long-lived open ISA with significant infrastructure support, including documentation, compiler tool chains, operating system ports, reference software simulators, cycle-accurate FPGA emulators, high-performance FPGA computers, efficient ASIC implementations of various target platform designs, configurable processor generators, architecture test suites, and teaching materials. Initial versions of all of these have been developed or are under active development. This material is to be made available under open-source licenses.

Getting Started

Download RISC-V software tools from our riscv-tools Github repository. This top-level repository includes the following components:
  • riscv-gcc, a RISC-V GCC cross-compiler
  • riscv-llvm, a RISC-V LLVM cross-compiler
  • riscv-isa-sim, the ISA simulator and "golden standard" of execution
  • riscv-pk, a proxy kernel that services system calls generated by code built and linked with the RISC-V newlib port
  • riscv-fesvr, a "front-end" server that services calls between the host and target processors on the Host-Target Interface (HTIF)
  • riscv-tests, a set of assembly tests and benchmarks
  • riscv-opcodes, the enumeration of all RISC-V opcodes
Other RISC-V software in external repositories:

Follow the RISC-V Toolchain Installation Manual for detailed instructions on how to build RISC-V software tools based on the RISC-V GCC/Newlib toolchain.

For those who want the Linux based RISC-V GCC/glibc toolchain and/or the full RISC-V Linux experience, follow the Linux/RISC-V Installation Manual for detailed instructions.

Funding

RISC-V has been developed as part of a number of sponsored research projects. We thank the following research sponsors for their support.

ASPIRE Lab: Research partially funded by:

Par Lab: Research supported by Microsoft (Award #024263) and Intel (Award #024894) funding and by matching funding by U.C. Discovery (Award #DIG07-10227). Additional support from Par Lab affiliates Nokia, NVIDIA, Oracle, and Samsung.

BWRC: Partially funded by DoE Award DE-SC0003624 (Project Isis).

The content of this website does not necessarily reflect the position or the policy of the US government or our other sponsors and no official endorsement should be inferred.

RISC-V News


Jul 2, 2014: A RISC-V port of GDB is now available at https://github.com/mythdraenor/riscv-gdb.git courtesy of Todd Snyder at Bluespec, Inc., enabling source-level debugging of C/C++ codes compiled for RISC-V.  For any questions about this, please email support@bluespec.com.


May 6, 2014: We are still working on the draft of the privileged ISA design, but hope to release early this summer for comments.


May 6, 2014: RISC-V User-Level ISA Version 2.0 is released! This document is also available as Technical Report UCB/EECS-2014-54. This represents the final frozen version of the base and standard extensions (IMAFD).


March 6, 2014: RISC-V LLVM is released at riscv-llvm.


March 5, 2014: Try out RISC-V Linux on ANGEL, our in-browser JavaScript ISA simulator.