The RISC-V Instruction Set Architecture

RISC-V (pronounced "risk-five") is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education, which we now hope will become a standard open architecture for industry implementations. RISC-V was originally developed in the Computer Science Division of the EECS Department at
the University of California, Berkeley.

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Why RISC-V? Our goals in defining RISC-V include:

A completely open ISA that is freely available to academia and industry.

A real ISA suitable for direct native hardware implementation, not just simulation or binary translation.

An ISA that avoids "over-architecting" for a particular microarchitecture style (e.g., microcoded, in-order, decoupled, out-of-order) or implementation technology (e.g., full-custom, ASIC, FPGA), but which allows efficient implementation in any of these.

An ISA separated into a small base integer ISA, usable by itself as a base for customized accelerators or for educational purposes, and optional standard extensions, to support general-purpose software development.

Support for the revised 2008 IEEE-754 floating-point standard.

An ISA supporting extensive user-level ISA extensions and specialized variants.

32-bit, 64-bit, and 128-bit address space variants for applications, operating system kernels, and hardware implementations.

An ISA with support for highly-parallel multicore or manycore implementations, including heterogeneous multiprocessors.

Optional variable-length instructions to both expand available instruction encoding space and to support an optional dense instruction encoding for improved performance, static code size, and energy efficiency.

A fully virtualizable ISA to ease hypervisor development.

An ISA that simplifies experiments with new supervisor-level and hypervisor-level ISA designs.

What's Available?

Right now, you can download the final user-level ISA specification, and RISC-V software tools including a GNU/GCC software tool chain, GNU/GDB debugger, an LLVM compiler, an ISA simulator, QEMU, and a verification suite.

The Sodor repository of educational RISC-V cores, written in Chisel is also available. The cores include a microcoded processor, an unpipelined processor, and 2, 3, and 5-stage pipelines. We plan to open-source our Rocket core (a 64-bit RISC-V single-issue in-order core) generator.

The zynq-fpga repository contains infrastructure for implementing Rocket cores on Zynq FPGAs, like the Zybo and ZedBoard.

To sample the architecture without installing anything, try out ANGEL, a JavaScript ISA simulator that boots an interactive session of riscv-linux on a simulated RISC-V machine in your browser.

Our intent is to provide a long-lived open ISA with significant infrastructure support, including documentation, compiler tool chains, operating system ports, reference software simulators, cycle-accurate FPGA emulators, high-performance FPGA computers, efficient ASIC implementations of various target platform designs, configurable processor generators, architecture test suites, and teaching materials. Initial versions of all of these have been developed or are under active development. This material is to be made available under open-source licenses.

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August 12, 2014: RISC-V at HotChips-26

The RISC-V team was out in force at the HotChips-26 conference manning a sponsor booth.

Yunsup arrives early on Sunday to set up the RISC-V booth.

Alongside a bunch of cool giveaways, including RISC-V buttons and bumper stickers, we had several demo boards at the conference. From left to right: a dual-core Rocket+Hwacha system in IBM's 45nm SOI process, running up to 1.35GHz, a single core Rocket+Hwacha system in ST 28nm FDSOI process running down to 0.45V, and an FPGA prototype running on a Xilinx Zybo board.

The Berkeley RISC-V team pose for a group shot at the end of the conference. From left to right: Steven Bailey, Henry Cook, Sagar Karandikar, Palmer Dabbelt, Krste Asanovic, Adam Izraelevitz, Colin Schmidt, Yunsup Lee, Andrew Waterman, Brian Zimmer, Scott Beamer, David Patterson.

August 7, 2014: RISC-V on EE Times

RISC-V: An Open Standard for SoCs, the case for an open ISA has been published on the EE Times Blog. It is also available as EECS Tech Report 2014-146.

July 29, 2014: RISC-V QEMU

Fast RISC-V System Emulation is now available via our QEMU port.

July 2, 2014: RISC-V GDB

A RISC-V port of GDB is now available on our downloads page, courtesy of Todd Snyder at Bluespec, Inc., enabling source-level debugging of C/C++ code compiled for RISC-V. For any questions about this, please email

May 6, 2014

We are still working on the draft of the privileged ISA design, but hope to release this summer for comments.

May 6, 2014: User-Level ISA v2.0 Released!

RISC-V User-Level ISA Version 2.0 is released! This document is also available as Technical Report UCB/EECS-2014-54. This represents the final frozen version of the base and standard extensions (IMAFD).