RISC-V (pronounced "risk-five") is a new instruction set architecture (ISA) designed to support computer architecture research and education. RISC-V was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley. Our goals in defining RISC-V include:
Right now, you can download the close-to-final user-level ISA specification, a draft of a supervisor ISA specification, and RISC-V software tools including a GNU/GCC software tool chain, an ISA simulator, and test codes.
Our intent is to provide a long-lived open ISA with significant infrastructure support, including documentation, compiler tool chains, operating system ports, reference software simulators, cycle-accurate FPGA emulators, high-performance FPGA computers, efficient ASIC implementations of various target platform designs, configurable processor generators, architecture test suites, and teaching materials. Initial versions of all of these have been developed or are under active development. This material is to be made available under open-source licenses.
riscv-toolsGithub repository. This top-level repository includes the following components:
riscv-gcc, a RISC-V cross-compiler
riscv-isa-sim, the ISA simulator and "golden standard" of execution
riscv-pk, a proxy kernel that services system calls generated by code built and linked with the RISC-V newlib port
riscv-fesvr, a "front-end" server that services calls between the host and target processors on the Host-Target Interface (HTIF)
riscv-tests, a set of assembly tests and benchmarks
riscv-opcodes, the enumeration of all RISC-V opcodes
Follow the RISC-V Toolchain Installation Manual for detailed instructions on how to build RISC-V software tools based on the RISC-V GCC/Newlib toolchain.
For those who want the Linux based RISC-V GCC/glibc toolchain and/or the full RISC-V Linux experience, follow the Linux/RISC-V Installation Manual for detailed instructions.
RISC-V has been developed as part of a number of sponsored research projects. We thank the following research sponsors for their support.
ASPIRE Lab: Research partially funded by:
Par Lab: Research supported by Microsoft (Award #024263) and Intel (Award #024894) funding and by matching funding by U.C. Discovery (Award #DIG07-10227). Additional support from Par Lab affiliates Nokia, NVIDIA, Oracle, and Samsung.
BWRC: Partially funded by DoE Award DE-SC0003624 (Project Isis).
The content of this website does not necessarily reflect the position or the policy of the US government and no official endorsement should be inferred.
August 26, 2013: Thanks to extensive feedback, we have been busy reworking the ISA spec, though this is taking longer than anticipated, so stay tuned for the next revision.
August 26, 2013: RISC-V poster at HotChips conference!
August 2, 2013: New draft ISA specification version 1.999 available. ISA will be frozen on August 16, so please send comments before then.
July 26, 2013: Draft website is up to public! Please provide feedback on the draft ISA specifications before the upcoming ISA freeze.