The RISC-V Exchange hosts the hardware, software, services, and learning offerings in the RISC-V community. Browse the list or search for an offering below.
Organization: Kai
An incomplete SoC
Software Type: Soft IP
Organization: Umm Al-Qura University
An Arabic course in Computer Architecture taught in RISC-V ISA based on Computer Organization and Design the Hardware/Software Interface, RISC-V Edition, David Patterson and John Hennessy by Dr. Ghassan F. Bati. http://www.uqu.edu.sa/gfbati
License Type: Copyleft
Learn Language: Arabic
Organization: BMRTech
This tutorial introduces basic background knowledge of IoT, IoT OS and RISC-V. Then it elaborates on the function of IoT OS kernel function and communication components. Application instances of GD32VF103 MCU and TencentOS tiny are presented.
License Type: Open custom
Learn Language: Chinese (Simplified)
This course is designed to provide the skills you need to build embedded systems with RTOS capabilities for real-time applications. Real time operating systems (RTOS) play an important role in any embedded system, enabling users to control the time critical functions required to be handled within specific timeframes for the effective use of those systems. FreeRTOS is an open source RTOS that has been used in various embedded systems and has been effectively ported onto various processors.
Learn Language: English
Organization: Czech Technical University in Prague
Classical Computer Architectures course using RISC-V as model architecture starting with number representation, building single cycle CPU, adding cache, pipeline, hazard unit,input output etc.. with demonstration on QtRvSim simulator with online version available.
License Type: Mixed
Learn Language: English
Organization: Cortus
We offer the Cortus Lotus1 MCU for consumer, general-purpose applications and motor control, with RISC-V processor core (with FPU and compressed mode instructions) and a comprehensive set of peripherals for embedded systems. The MCU has flexible power management suitable for permanently on battery powered devices. We offer not only chips, but a complete ready-to-use solution including a full SDK with RTOS and peripheral device drivers as well as a development board.
Organization: UC3M
CREATOR: didaCtic and geneRic assEmbly progrAmming simulaTOR
Software Type: Simulators
Organization: Deepcomputing
With native cutting-edge features, our ROMA laptop lets users directly expand and explore the RISC-V ecosystem. Our ambition is to make 2022 a special year for all those facing the many issues of living and working in our post-Covid world. Which is why we are delighted to be able to join together with our partners to create this breakthrough in RISC-V SoC development. We know the launch of the ROMA laptop will bring an exciting new frontier to our many customers. Please follow our weekly blog for the latest news on ROMA and our exciting new products and peripherals.
Organization: Deepcomputing
1. Built-in varistor，excellent EMC performance. 2. Reduces shock and impact, adapting complex road conditions. 3. Strong grip,RoHS material. 4. Smooth steering experience. 5. The response speed is 2X faster than common analogservo. The servo will be released after being blocked for 5seconds.Precise steering control, response time <11 ms. 6. Power by RISC-V.
Organization: Digital Core Design
DCD’s RV32IMZicsr RISC-V Core The DRV32IMZicsr is a 32-bit RISC-V CPU with M, Zicsr extensions, and External Debug support. The Core belongs to the latest DCD’s DRVX Core Family, with: a five-stage pipeline, Harvard architecture flexible size of program and data memory together with their allocation in address space. It is possible to select CPU interface as: AXI, AHB, Native. The DRV32IMZicsr was developed as ISO26262 Safety Element out of Context (SEooC) and is technology independent, and compatible with all FPGA and ASIC vendors. The DRV32IMZicsr can be used along with a wide range of DCD’s peripherals, like e.g. DMA, SPI, UART, PWM, CAN etc. This holistic approach makes the DRV32IMZicsr core a good choice for application for e.g. Automotive, Internet of Things, Embedded, Consumer Electronics, and more. The DRV32IMZicsr is a 32-bit core with 32 General Purpose Registers. It performs arithmetic and logic instructions, loads, stores, conditional branches, and unconditional jumps. The proper usage of base instructions provides an additional set of pseudo instructions which are available in the RISC-V assembly language. The M extension enables the use of additional integer multiplication and division instructions due to Multiplication and Division unit, which is responsible for handling these instructions. The Zicsr extension provides the means to access Control and Status Registers, which in turn enables interrupt and exception handling according to version 20211203 of The RISC-V Instruction Set Manual Volume II: Privileged Architecture. With Zicsr extension DRV32IMZicsr core is also equipped with performance counters and timers. External Debug support utilizes JTAG debug interface and is implemented with conformance to the RISC-V Debug Specification 0.13.2 and 1.0.0. That allows core debugging with all the tools compatible with this specification available on the market. The DRV32IMZicsr core is delivered with a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of the SoC design flow. DESIGN FEATURES: ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G. Altera / Intel, Xilinx / AMD, Lattice, Microsemi / Microchip, and others. TSMC UMC SK Hynix and others.
Software Type: Soft IP
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