Allen Baum

Senior Architect, Esperanto

Allen is a Senior Architect at Esperanto.

Avi Timor

CPU Architecture and Design, Google

Avi works in CPU Architecture and Design at Google.

Bob Brennan

Vice President of Customer Solutions Engineering, Intel Foundry Services at Intel Corporation

Bob Brennan is Vice President of Customer Solutions Engineering for Intel Foundry Services at Intel Corporation. He is responsible for leading the delivery of end-to-end design solutions to help IFS customers use Intel’s portfolio of unique IPs and design technology in their product designs. This responsibility covers the entire design life cycle for customers, from customer design architecture to the strategic selection of Intel IP to platform enablement, as well as design services support for SoC integration including validation and debug support. In his previous role, Bob served as Vice President of Emerging Memory & System at Micron, where he managed product, design, and engineering teams to accelerate the delivery of new designs on new technologies. Bob also served as Senior Vice President of Memory Solutions Lab at Samsung, where he established an Enterprise SSD product line, delivered Samsung’s first revenue software product while continuing an active role in architecture development. Prior to these roles, Bob spent 22 years at Intel serving in various senior technical positions, including Server Architecture, Laptop Architecture, Mobile SoC Architecture, and CPU Core Design, Verification and Architecture.

Charlie Su

CTO and President, Andes Technology Corporation

Charlie is CTO and President at Andes Technology Corporation.

David Brash

Assistant GM, Rivos Systems UK Ltd.

David is Assistant GM at Rivos Systems UK Ltd.

David Chen

Head of Technical Operation, Alibaba Cloud

Dr. David(Wei) Chen is the Head of Technical Operations of CPU Product at Alibaba T-Head, mainly focus on building RISC-V CPU ecosystem. He is also the vice chair of Application and Tools HC in RISC-V International.

Before that David was the director of Arm education program in APAC and then China, his interests are academic projects on embedded systems, IOT, and AI technology. David also has professional positions in several top universities in China. He received his MS and PhD degrees in Mechanical Engineering from Michigan Technological University.

David Weaver

Principal Architect, Akeana

Akeana is (so far) a stealth-mode company, actively developing in the RISC-V space.  Dave began his career creating cross-development tools for embedded processors, then served as an ISA Architect for another UCB RISC-based architecture (SPARC) at Sun & Oracle.  There, he was responsible for the architectural consistency, architecture specifications, opcode space management, and coordination of all ISA extensions for 20+ yrs.  That work required collaboration across many technical disciplines and multiple companies.  He also served for 7 years as a Director on the Board of SPARC International (an organization parallel to RISC-V International).  After that, he served in the Architecture Research department at Arm, then in 2021 joined Akeana.

Earl Killian

CTO, Aril Inc

Earl is CTO of Aril Inc. In his career he has worked as a software engineer (operating systems, compilers, and networking) and microprocessor architect. He graduated from MIT in 1978 (B.S. Electrical Engineering and Computer Science), first working on software at BBN and LLNL, and subsequently in software and microprocessor design at MIPS, QED, SGI, and Tensilica, all silicon valley companies engaged in creating microprocessor products for both general-purpose and embedded computing as well as some experience in HPC. Earl was a co-founder and CTO of QED, and held the title Director of Architecture at each of the other companies. His microprocessor work has resulted in 34 patents issued so far. He has been involved in the specification of several Instruction Set Architectures.

Fan Xiaobo

Co-Founder, Stream Computing

Shawn is the co-founder of Stream Computing Inc. which is a startup company using RISC-V ISA to develop high power-efficiency and programmable DSA AI Processor. 

He has 20 years of experience in the IC industry, covering the entire process of IC architecture, design, verification and implementation, as well as rich Product development, project and team management experience.

He led the his team complete the cumulative shipment of more than 300 million mobile phone chips, mass production of a 400mm2 server CPU based on Samsung’s 10nm process, and Successfully taped out a cloud AI inference chip based on TSMC’s 12nm process in Stream Computing Inc.

Gajinder Panesar

Chief Architect, Picocom

Gajinder is Chief Architect at Picocom.

Haibin Shen

Chengwei Capital

Haibin is with Chengwei Capital

Jack Li

Haihe Laboratory of IT

Dr. Jack Li has been working in the field of high performance computing and heterogeneous acceleration for a long time. He has in-depth research in the fields of high-performance architecture design, operating system design, compiler optimization, general data compression technology, and heterogeneous computing acceleration systems for genetics and bioinformatics. He has published numerous papers in conferences and journals such as PACT, PPoPP, USENIX Security, Cell Genomics and holds several patents.

James Ball

Platform Architect, Qualcomm

James Ball is a member of the Qualcomm platform architecture team in San Diego. He is an industry veteran with over 30 years of experience primarily in computer architecture, ISA design, and embedded processor architecture & design. 20 years ago James created the FPGA-optimized Nios II RISC instruction set and processor cores while at Altera (now part of Intel). He joined the FPGA architecture team and before leaving Intel 2 years ago to join Qualcomm he created a proof of concept for Nios V (RISC-V version). Before Intel, James worked at ARC International (now part of Synopsys) on microcontroller & trace RTL design, Xerox PARC as an ASIC architecture & RTL designer for imaging processing ASICs, and Sun Microsystems in the SPARC architecture team and UltraSPARC III RTL design. He holds over 15 patents in the areas of CPU architecture, FPGA architecture, trace, and image processing. James is originally from Canada (graduated from University of Waterloo) but now considers California his home.

Ji Dong

IC Engineer, Sanechips/ZTE

Ji is an IC Engineer at Sanechips/ZTE.

Jianlin Gao

Director, Tencent

Jianlin Gao is the Director of panglai laboratory in Tencent . He is a expert in IC and OS software, developed the edge AI chip“penglai” and cloud side AI chip “zixiao” as main architect , also designed the codec chip “canghai”, support H265 and H266 encode.

John Leidel

Chief Scientist/Founder at Tactical Computing Laboratories

Dr. John Leidel is the Chief Scientist and Founder of Tactical Computing Laboratories where he leads efforts in developing advanced architectural and programming model techniques for scalable high performance and data intensive computing platforms. Dr. Leidel is currently the PI for several funded efforts to extend the RISC-V architecture for various high performance, data intensive computing platforms.

Kan Shi

Associate Professor, Chinese Academy of Sciences

Dr. Kan Shi is currently an Associate Professor at the Institute of Computing Technology, Chinese Academy of Sciences. His research interests include agile chip design, reconfigurable computing, and cloud data center architecture.

Dr. Shi earned his PhD from Imperial College London, and then worked at Intel UK R&D center as an SoC Design Engineer, with focus on developing FPGA-based SmartNIC/DPU/IPU and their applications in cloud data centers.

Nick Kossifidis

Principal Research Engineer, ICS-FORTH

Nick Kossifidis is a principal research engineer at the FORTH research center in Greece, with extensive experience in networking, systems software, and security. He has worked as an IT security consultant and penetration tester for Fortune 500 companies on high profile projects, and is an active contributor on security and software related topics within the RISC-V technical committee and the RISC-V community in general. Nick has multiple contributions in open source projects, including various subsystems of the Linux kernel, and is currently working on the bringup, validation, and optimization process of various RISC-V prototypes of the European Processor Initiative (EPI). He is also an activist and open source advocate, with an interest in community wifi networks and radio stations, open governance, and privacy.

Ozgur Ozkurt

Senior Director of CPU Hardware Engineering, Imagination Technologies

Ozgur Ozkurt is Senior Director of Engineering of CPU at Imagination Technologies responsible for all RISC-V processors development across Imagination since October 2021. Previously, he was managing engineering teams at Arm in CPU and Display processor products; also, has been a technical lead for various Display and Image Signal Processor products since 2013. Prior to Arm, Ozgur was a research engineer at Vestek working on various computer vision algorithms and their hardware implementations used in 3D TVs and gesture recognition.

At Arm, he was a member of the Design Steering Committee, ensuring consistency in quality and PPA analysis across all product lines. He has been a member of the VESA and HDMI Consortiums. He has experience on FUSA processor development and overall system performance analysis. He earned his MSc in EE on Embedded Video Systems in 2012 from BAU Istanbul.

Peter Chun

Director of Technical Planning & Research Collaboration, Huawei

Peter is Director of Technical Planning & Research Collaboration at Huawei.

Philipp Tomsich

Chief Technologist & Founder, VRULL GmbH

Dr. Philipp Tomsich is the Chief Technologist and Founder of VRULL, an engineering consultancy focused on building, enabling, and optimizing the software ecosystems for next-generation silicon solutions.

Sergey Yakushkin

Director of Software Engineering, Syntacore

Sergey Yakushkin is the Director of Software Engineering at Syntacore, a company developing microprocessor IP based on RISC-V architecture. He has more than 15 years of experience in compilers, code-generation and optimizations for novel ISA and processor micro-architecture, debugging, profiling and simulation tools, design of domain-specific and architecture description languages for retargetable tools and hardware-software co-design. He has worked at academia and major companies including Intel, RWTH, Huawei, and Synopsys and has participated in and published papers for conferences such as LLVM, DATE, DAC, HPCA.

Stacey Secatch

Principal Engineer, Seagate Technology

Stacey Secatch is a Principal Engineer at Seagate Technology, the global leader in data storage systems. She is a Performance Architect for the RISC-V program at Seagate. Past roles at Seagate include System Architecture and Firmware Development for Seagate SSDs. Prior to that, she specialized in verification: publishing numerous papers and participating in the UVM specification effort. Stacey received a Bachelor of Science in Engineering from the University of Michigan and a Master of Engineering from Colorado State University.

Wei Wu

Co-founder & Project Director, PLCT Lab, ISCAS

Wei Wu is the co-founder and project director of the PLCT Lab. Under his leadership, the PLCT Lab is contributing to RISC-V ecosystem, especially in GNU Toolchain, LLVM, V8, QEMU and AOSP. He is the chairman of the OSDT working group, which is an active community focusing on open source developer tools and projects. He is passionate about pushing the boundary of the RISC-V ecosystem.

Dr. Yungang Bao

Chief Scientist, Beijing Institute of Open Source Chip

Yungang Bao is a Professor of Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) and the director of Research Center of Advanced Computer Systems (ACS) of ICT-CAS. Prof. Bao founded China RISC-V Alliance (CRVA) and serves as the secretary-general of CRVA. His research interests include computer architecture and computer systems. His research work such as Labeled von Neumann Architecture (LvNA), Hybrid Memory Trace Tool (HMTT), Partition-Based DMA Cache and PARSEC 3.0 has been adopted by the industry including Alibaba, Huawei, Intel and the research community. He was a plenary keynote speaker at China National Computer Congress (CNCC) in 2016 and was invited to give a keynote presentation at ARM Research Summit 2018. He was the winner of CCF-Intel Young Faculty Award of the year for 2013. He won CCF-IEEE CS Young Computer Scientist Award and China’s National Lofty Honor for Youth under 40 of the year for 2019.

Dr. Zhangxi Tan

Co-Director, RIOS Laboratory

Dr. Zhangxi Tan is a co-director of the RISC-V International Open-source Laboratory (RIOS), leading open-source IP and software development that helps the RISC-V ecosystem world-class. Dr. Tan is an adjunct professor at Tsinghua-Berkeley Shenzhen Institute (TBSI). He received his PhD in computer science from UC Berkeley in 2013. He is specialized in computer architecture and VLSI designs. After graduating from Berkeley, he joined Pure Storage (NYSE: PSTG) as a Founding Engineer serving as a lead designer for Pure’s award winning FlashBlade product, which generates hundreds of million-dollar revenues every year and have many high-profile customers. Dr. Tan holds more than 20 US patents in flash storage systems and hardware accelerators. He also founded several startup companies in Silicon Valley and China in the chip design industry.