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We send occasional news about RISC-V technical progress, news, and events.
Chief Technologist & Founder, VRULL GmbH
Dr. Philipp Tomsich is the Chief Technologist and Founder of VRULL, an engineering consultancy focused on building, enabling, and optimizing the software ecosystems for next-generation silicon solutions.
Head of Technical Operation, Alibaba Cloud
Dr. David(Wei) Chen is the Head of Technical Operations of CPU Product at Alibaba T-Head, mainly focus on building RISC-V CPU ecosystem. He is also the vice chair of Application and Tools HC in RISC-V International.
Before that David was the director of Arm education program in APAC and then China, his interests are academic projects on embedded systems, IOT, and AI technology. David also has professional positions in several top universities in China. He received his MS and PhD degrees in Mechanical Engineering from Michigan Technological University.
Principal Architect, Akeana
In Dave’s early career, he led a team developing software cross-development tools for embedded processors. He became as ISA Architect for another UCB RISC-derived architecture (SPARC), where he was responsible for architectural consistency, architecture specifications, opcode space management, and coordination of all ISA extensions for 20+ yrs. That work required collaboration across many technical disciplines (and multiple companies). He served for 7 years as a Director on the Board of SPARC International (similar to RISC-V International). After that, he worked in Architecture Research at Arm for a few years. He currently serves as a Principal Architect at Akeana and participates in numerous RISC-V SIGs and technical Task Groups.
CTO, Aril Inc
Earl is CTO of Aril Inc. In his career he has worked as a software engineer (operating systems, compilers, and networking) and microprocessor architect. He graduated from MIT in 1978 (B.S. Electrical Engineering and Computer Science), first working on software at BBN and LLNL, and subsequently in software and microprocessor design at MIPS, QED, SGI, and Tensilica, all silicon valley companies engaged in creating microprocessor products for both general-purpose and embedded computing as well as some experience in HPC. Earl was a co-founder and CTO of QED, and held the title Director of Architecture at each of the other companies. His microprocessor work has resulted in 34 patents issued so far. He has been involved in the specification of several Instruction Set Architectures.
Vice President of Hardware Engineering, NVIDIA
Frans Sijstermans earned his MSc degree in Computer Science from the Eindhoven University of Technology in 1985. He worked as a researcher at Philips in The Netherlands and Palo Alto, USA, until 1998. After that he held various managerial positions at Philips Semiconductors, TriMedia, and Equator. He joined NVIDIA in 2004, where he is responsible for all RISC-V processors, security IP, video codecs, camera & display controllers, vision & DL accelerators, and GSYNC products. He has been active in the open source community as a member of the inaugural board of the RISC-V foundation and the Alliance for Open Media. Also, his team open sourced NVDLA, NVIDIA’s inferencing accelerator.
Director, Stream Computing
Dr. Fujie Fan is the Research & Development Director of Stream Computing. He is leading the ISA development and standardization for RISC-V based AI processor. As an architect, he designed the RISC-style Matrix ISA of Stream Computing, and provided a high-performance open-source implementation for RISC-V Vector/Matrix extensions. His research areas mainly focus on AI chip design, computer architecture and RISC-V hardware/software ecosystem.
Guy has been a Professor in Computer Engineering at the University of British Columbia for over 20 years where I teach advanced digital design and computer systems/architecture related courses. My undergrad and graduate degrees are all from the University of Toronto. I’ve built processors from scratch (RISC-V and others), co-founded VectorBlox Computing where we developed the MXP (Matrix Processor) as a vector accelerator for RISC-V and other ISAs. In grad school, I co-designed custom designed cache-coherent multiprocessors that were built from MIPS R4400 CPUs and custom PCBs and FPGA circuitry. My research focuses on improving FPGA devices and CAD tools, in particular making them easier to use for computing tasks. I was a member of the RISC-V Vector Committee and the early Cache Management Operations committee, and I chair the RISC-V SoftCPU SIG. I’ve also given several talks at RISC-V meetings.
Platform Architect, Qualcomm
James Ball is a member of the Qualcomm platform architecture team in San Diego. He is an industry veteran with over 30 years of experience primarily in computer architecture, ISA design, and embedded processor architecture & design. 20 years ago James created the FPGA-optimized Nios II RISC instruction set and processor cores while at Altera (now part of Intel). He joined the FPGA architecture team and before leaving Intel 2 years ago to join Qualcomm he created a proof of concept for Nios V (RISC-V version). Before Intel, James worked at ARC International (now part of Synopsys) on microcontroller & trace RTL design, Xerox PARC as an ASIC architecture & RTL designer for imaging processing ASICs, and Sun Microsystems in the SPARC architecture team and UltraSPARC III RTL design. He holds over 15 patents in the areas of CPU architecture, FPGA architecture, trace, and image processing. James is originally from Canada (graduated from University of Waterloo) but now considers California his home.
Jianlin Gao is the Director of panglai laboratory in Tencent . He is a expert in IC and OS software, developed the edge AI chip“penglai” and cloud side AI chip “zixiao” as main architect , also designed the codec chip “canghai”, support H265 and H266 encode.
SW Product Management Director at Intel Corporation
John is SW Product Management Director at Intel Corporation.
Chief Scientist/Founder at Tactical Computing Laboratories
Dr. John Leidel is the Chief Scientist and Founder of Tactical Computing Laboratories where he leads efforts in developing advanced architectural and programming model techniques for scalable high performance and data intensive computing platforms. Dr. Leidel is currently the PI for several funded efforts to extend the RISC-V architecture for various high performance, data intensive computing platforms.
Associate Professor, Chinese Academy of Sciences
Dr. Kan Shi is currently an Associate Professor at the Institute of Computing Technology, Chinese Academy of Sciences. His research interests include agile chip design, reconfigurable computing, and cloud data center architecture.
Dr. Shi earned his PhD from Imperial College London, and then worked at Intel UK R&D center as an SoC Design Engineer, with focus on developing FPGA-based SmartNIC/DPU/IPU and their applications in cloud data centers.
Senior Principal Architect, Tenstorrent
Ken is passionate about RISC-V and all of its potential! Since 2018 he has served on the Board of Directors, headed several Task Groups, authored several ISA extensions, contributed to many TGs & SIGs, and made multiple presentations at RISC-V Summits and Workshops. In his day job, he has played a key role in the development and optimization of several RISC-V implementations.
Ken is a Senior Principal Architect at Tenstorrent where he defines high-end RISC-V processors and systems.
Ken has over 36 years of experience in computer architecture and development, and has over three dozen patents.
Ken is currently a member of SPEC OSG and IEEE P3109 (Arithmetic Formats for Machine Learning). He has also contributed to the development of the IEEE-754 Floating-Point Standard.
Senior Director of CPU Hardware Engineering, Imagination Technologies
Ozgur Ozkurt is Senior Director of Engineering of CPU at Imagination Technologies responsible for all RISC-V processors development across Imagination since October 2021. Previously, he was managing engineering teams at Arm in CPU and Display processor products; also, has been a technical lead for various Display and Image Signal Processor products since 2013. Prior to Arm, Ozgur was a research engineer at Vestek working on various computer vision algorithms and their hardware implementations used in 3D TVs and gesture recognition.
At Arm, he was a member of the Design Steering Committee, ensuring consistency in quality and PPA analysis across all product lines. He has been a member of the VESA and HDMI Consortiums. He has experience on FUSA processor development and overall system performance analysis. He earned his MSc in EE on Embedded Video Systems in 2012 from BAU Istanbul.
Director of Technical Planning & Research Collaboration, Huawei
Peter is Director of Technical Planning & Research Collaboration at Huawei.
Founder and CEO, Semidynamics
Roger Espasa is the founder and CEO of Semidynamics, an IP supplier of two RISC-V cores, Avispado (in-order) and Atrevido (out-of-order) supporting the RISC-V vector extension and Gazzillion TM misses, both targeted at HPC and Machine Learning. In addition, Semidynamics architected and designed the Esperanto Technologies 1024 core machine-learning 7nm SoC. Prior to Semidynamics, Roger was at Broadcom working on an ARMV8 wide out-of-order core. (2014-2016). Previously, Roger worked at Intel (2002-2014) developing a vector extension for the x86 ISA, initially deployed in XeonPhi (Larrabee) which then became AVX-512. Roger also led the texture sampling unit for Larrabee. Roger then worked on Knights Landing (14nm) and led the core for Knights Hill (10nm). Between 1999 and 2001 Roger worked for the Alpha Microprocessor Group on a vector extension to the Alpha architecture known as Tarantula. Roger got his PhD from UPC in 1997, has published over 40 peer-reviewed papers on Vector Architectures, Graphics/3D Architecture, Binary translation and optimization, Branch Prediction, and Media ISA Extensions and holds 9 patents with 41 international filings.
Director of Software Engineering, Syntacore
Sergey Yakushkin is the Director of Software Engineering at Syntacore, a company developing microprocessor IP based on RISC-V architecture. He has more than 15 years of experience in compilers, code-generation and optimizations for novel ISA and processor micro-architecture, debugging, profiling and simulation tools, design of domain-specific and architecture description languages for retargetable tools and hardware-software co-design. He has worked at academia and major companies including Intel, RWTH, Huawei, and Synopsys and has participated in and published papers for conferences such as LLVM, DATE, DAC, HPCA.
Vice President of Architecture, SiFive
Dr. Shubu Mukherjee is SiFive’s VP of Architecture. Shubu is the winner of the ACM SIGARCH Maurice-Wilkes award in 2009, winner of the MICRO Test of Time award in 2022, a Fellow of ACM, a Fellow of IEEE, and the author of the book, “Architecture Design for Soft Errors.” Shubu holds 100+ patents and has written over 50+ technical papers in top architecture conferences and journals. Before joining SiFive in December 2019, Shubu worked at Marvell, Cavium, Intel, and Compaq for 21 years. He received his MS and Phd from the University of Wisconsin-Madison and his B.Tech. from the Indian Institute of Technology, Kanpur.
Principal Engineer, Seagate Technology
Stacey Secatch is a Principal Engineer at Seagate Technology, the global leader in data storage systems. She is a Performance Architect for the RISC-V program at Seagate. Past roles at Seagate include System Architecture and Firmware Development for Seagate SSDs. Prior to that, she specialized in verification: publishing numerous papers and participating in the UVM specification effort. Stacey received a Bachelor of Science in Engineering from the University of Michigan and a Master of Engineering from Colorado State University.
Co-founder & Project Director, PLCT Lab, ISCAS
Wei Wu is the co-founder and project director of the PLCT Lab. Under his leadership, the PLCT Lab is contributing to RISC-V ecosystem, especially in GNU Toolchain, LLVM, V8, QEMU and AOSP. He is the chairman of the OSDT working group, which is an active community focusing on open source developer tools and projects. He is passionate about pushing the boundary of the RISC-V ecosystem.
Chief Scientist, Beijing Institute of Open Source Chip
Yungang Bao is a Professor of Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) and the director of Research Center of Advanced Computer Systems (ACS) of ICT-CAS. Prof. Bao founded China RISC-V Alliance (CRVA) and serves as the secretary-general of CRVA. His research interests include computer architecture and computer systems. His research work such as Labeled von Neumann Architecture (LvNA), Hybrid Memory Trace Tool (HMTT), Partition-Based DMA Cache and PARSEC 3.0 has been adopted by the industry including Alibaba, Huawei, Intel and the research community. He was a plenary keynote speaker at China National Computer Congress (CNCC) in 2016 and was invited to give a keynote presentation at ARM Research Summit 2018. He was the winner of CCF-Intel Young Faculty Award of the year for 2013. He won CCF-IEEE CS Young Computer Scientist Award and China’s National Lofty Honor for Youth under 40 of the year for 2019.
Co-Director, RIOS Laboratory
Dr. Zhangxi Tan is a co-director of the RISC-V International Open-source Laboratory (RIOS), leading open-source IP and software development that helps the RISC-V ecosystem world-class. Dr. Tan is an adjunct professor at Tsinghua-Berkeley Shenzhen Institute (TBSI). He received his PhD in computer science from UC Berkeley in 2013. He is specialized in computer architecture and VLSI designs. After graduating from Berkeley, he joined Pure Storage (NYSE: PSTG) as a Founding Engineer serving as a lead designer for Pure’s award winning FlashBlade product, which generates hundreds of million-dollar revenues every year and have many high-profile customers. Dr. Tan holds more than 20 US patents in flash storage systems and hardware accelerators. He also founded several startup companies in Silicon Valley and China in the chip design industry.
We send occasional news about RISC-V technical progress, news, and events.