Frequently Asked Questions (FAQ)

The RISC-V ISA is free and open with a permissive license for use by anyone in all types of implementations. Designers are free to develop proprietary or open source implementations for commercial or other exploitations as they see fit. RISC-V International encourages all implementations that are compliant to the specifications.

Note that the use of the RISC-V trademark requires a license which is granted to members of RISC-V International for use with compliant implementations. The RISC-V specification is based around a structure which allows flexibility with modular extensions and additional custom instructions/extensions. If an implementation was based on the RISC-V specification but includes modifications beyond this framework, then it cannot be referenced as RISC-V.

The RISC-V ISA is free for product use too. Those who want to use the RISC-V logo should join RISC-V International (see question No. 1).

No, the source code can be completely closed.

Yes. Both the RISC-V Unprivileged (user-level) ISA and Privileged ISA are available as tech reports. In addition, there is a Debug Specification available.

Yes. Visit our Proceedings Page and Google Scholar to learn more.

There are a wide variety of software tools available; proceed to the Software Tools page to see a list.

We plan to define more optional instruction set extensions for RISC-V beyond the ones we already have, including Packed-SIMD Instructions (P), Bit Manipulation (B), Decimal Floating-Point (L) and Transactional Memory (T). One goal for RISC-V International is to manage development of these future standard instruction set extensions.

The currently defined extensions to the base Integer (I) ISA are Multiply-Divide (M), Atomic (A), Floating-point in multiple precisions (F, D, and Q), and Compressed Instructions (C).

This depends entirely on the quality of the implementation, including microarchitectural design, circuit design and process technology used. We believe there are no fundamental reasons that a RISC-V implementation should be less efficient than x86 or Arm, and indeed that the ISA design should enable implementations to be somewhat more efficient than either.

This depends entirely on the quality of the implementation, but we feel RISC-V implementations should be at least comparable in energy efficiency to Arm cores built in the same microarchitectural style and with the same engineering effort in the same process technology.

RISC-V International Vendor ID assignment uses JEDEC manufacturer IDs as defined in the RISC-V ISA Privileged Architecture Specification v1.10 Section 3.1.2 Machine Vendor ID Register mvendorid and repeated here for convenience.  Refer to the full Privileged Architecture Specification here.

3.1.2 Machine Vendor ID Register mvendorid

The mvendorid CSR is an XLEN-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. This register must be readable in any implementation, but a value of 0 can be returned to indicate the field is not implemented or that this is a non-commercial implementation.