Board of Directors

Ken continues to be passionate about RISC-V and all of its potential!

Since 2018 he has actively contributed to the RISC-V community through serving on the Board of Directors and the Technical Steering Committee, heading several Task Groups, authoring several ISA extensions, contributing to many TGs & SIGs, and making multiple presentations at RISC-V Summits and Workshops. In his day job, he has played a key role in the development and optimization of several RISC-V implementations.

Ken is a Senior Principal Architect at Tenstorrent where he defines high-end RISC-V processors and systems.

Ken has over 37 years of experience in computer architecture and development, and has over three dozen patents.

When not helping develop the RISC-V architecture, implementing RISC-V designs, helping develop new floating point standards (IEEE P3109 and IEEE-754), or developing processor benchmarks (SPEC OSG), Ken can be found spending time with family, fiddling with antique phonographs, and playing classical guitar.

Lu Dai is a Vice President of Technical Standards at Qualcomm Technologies, Inc., where he leads global compute standards initiatives and fosters strategic relationships with industry organizations.  

Previously, Lu served as Senior Director of Engineering, heading Qualcomm’s SoC design verification team and driving front-end methodologies and innovation. He was the Design Verification Lead for multiple generations of Qualcomm’s premium-tier platforms, including the Snapdragon 8 series and technologies that power NASA’s Mars Perseverance rover and Ingenuity helicopter.   

Before joining Qualcomm, Lu was the Design Verification Lead for Cisco’s Gigabit Switching Business Unit, contributing to several generations of Cat4k ASICs.  

Lu is deeply involved in industry standards leadership. He is the Chair of Accellera, Chairman of the RISC-V International Board of Directors, and serves as a Board Officer at Si2. 

He holds a Master’s degree in Electrical Engineering from Cornell University and a Bachelor’s degree in Electrical Engineering and Computer Science from UC Berkeley.

Dr. Philipp Tomsich is Chief Technologist and Founder of VRULL, a company providing outsourced R&D for semiconductor companies: services range from tools for pre-silicon architectural exploration to the building of software ecosystems .

Stefan is a professor at Munich University of Applied Sciences. He is a long term advocate and active member of the open source silicon community, most prominent in his role as director of the Free and Open Source Silicon Foundation (FOSSi Foundation). He has been active in various RISC-V projects over the last six years. Stefan was involved in the debug task group and has recently become chair of the RISC-V SIG “Academia & Education”.

Dr. Ning He is the Senior Vice President and Chief Technology Officer of ESWIN Computing Technology Co. Ltd, a leading RISC-V product and solution provider in China. He holds a Bachelor‘s and a Master’s degree from the University of Electronic Science and Technology of China, and a Ph.D. degree in Electrical Engineering from Arizona State University, USA. Prior to joining ESWIN, Dr. He served as Vice President and CTO at a company listed on China’s A-share market. With extensive expertise in telecommunication systems, IC system & architecture design, and technology management, he now leads the development of RISC-V ecosystem and technology platforms at ESWIN. Beyond his corporate role, Dr. He also serves as the rotating chairman of the RISC-V Working Committee at the China Electronics Standardization Association, and as a board member of several other influential organizations. 

Cesc holds a PhD in Architecture and Computer Science. He spent 5 years at the Barcelona Supercomputing Center performing research on HPC. He holds more than 60 publications and has been tutoring multiple PhDs during his career.

After that, he moved to Intel. First,  Cesc was in the Intel Product Group for 7 years working as a Hardware Architect (including CPU architecture, design, and performance modeling).

Afterwards, he moved into the Intel Data Center and AI division for 6 years. While continuing work on the product architecture, Cesc expanded his areas of work into Hardware and Software System Architecture focusing on things like Platform & Rack designs, Orchestration, Power management, etc. Cesc for his last years at Intel has been a Senior Principal Engineer and the Network and Edge Chief System Architect in the Network and Edge Intel CTO Office.

He led a global group of architects from various verticals (retail, transportation, industrial, network, etc.).  While driving architecture he has been working with industry partners and business organizations for more than a decade. He was responsible for defining system-level designs across the NEX division and driving future Intel technologies and platform requirements for Edge (XPU, IPU, system architecture). His work included influence as well as working with open-source initiatives, partners, and end-customers to realize the system architecture. While driving revenue and business for Intel, Cesc has been having important focus on product definition, innovation, and technology design. He holds more than 500 patents, has been the lead architect in multiple Intel products, and has been top Intel Inventor during 2019, 2020, 2021, 2022, and 2023.

Last, but not least, Cesc transitioned as a Chief Executive Officer at Openchip with the ambition to continue his work in the creation and delivery of system-focused products and designs with the aim of solving end-users problems. In this new mission, Cesc is laser focused to contribute to Europe’s technology sovereignty while providing solutions that aim to help and improve European citizens’ lives. For example, one of the critical mission statements mid-long term goals for Openchip is to democratize access to AI with mechanisms that allow data privacy and protection.

Frank has received his B.Sc. and M.Sc. from the Istanbul Technical University, and his Ph.D degree from ETH Zurich. He is a senior scientist in the group of Luca Benini and is the director of the Microelectronics Design Center at ETH Zurich. He has been part of the PULP platform project since its beginning in 2013 and has been actively involved in RISC-V and open source activities.

Frankwell Lin is the President and co-founder of Andes Technology, which is a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores. Frankwell received BSEE degree of Electrophysics from the National Chiao-Tung University, Taiwan, and MSEE degree of Electrical and Computer Engineering from Portland State University, Oregon, USA. Before Andes Technology, he was the spokesperson and board member of Farady, a leading fabless ASIC and silicon IP provider. He also led ASIC business development as starting, then on-and-off leading ASIC implementation, chip backend service, IP business development, industry relationship development (IR) in Faraday. Under his management, Andes Technology has been recognized as one of leading suppliers of embedded CPU IP in semiconductor industry. Andes also won the reputation of leading technology company with awards such like 2012 EE Times worldwide Silicon 60 Hot Startups to Watch, 2015 the Deloitte Technology Fast 500 Asia Pacific award, etc. In 2015, President Lin received accolade award of Outstanding Technology Management Performance, Taiwan, for his contribution to the high-tech industry. In parallel to contribution in the industry, he also contributes time and effort in social service for technology evolution. He is Chairman of TEIA (Taiwan Embedded Industry Alliance) from 2010 to 2012. TEIA is a non-profit organization to promote embedded system innovation as well as embedded system value chain engineering talent training, including embedded software, hardware, IP, application, international promotion channel, etc.

Frans Sijstermans earned his MSc degree in Computer Science from the Eindhoven University of Technology in 1985. He worked as a researcher at Philips in The Netherlands and Palo Alto, USA, until 1998. After that he held various managerial positions at Philips Semiconductors, TriMedia, and Equator. He joined NVIDIA in 2004, where he is responsible for all RISC-V processors, security IP, video codecs, camera & display controllers, vision & DL accelerators, and GSYNC products. He has been active in the open source community as a member of the inaugural board of the RISC-V foundation and the Alliance for Open Media. Also, his team open sourced NVDLA, NVIDIA’s inferencing accelerator.

Dr. Henry He is the Director of Operations at Phytium Technology. He used to be a processor R & D engineer and worked in the field of computer architecture for more than ten years. At present, he is engaged in some management work, and responsible for the marketing management that includes product planning, technical planning and marketing strategy. He likes making friends and singing.

Jefro has been deeply involved in the RISC-V effort for many years. He worked for RISC-V Foundation, and then RISC-V International, from 2019 to 2021 and oversaw several initiatives on the technical side as well as member management and community development. Jefro was also the board secretary during this time. Since moving over to Red Hat in 2021, he has been an advocate for RISC-V software development within Red Hat as well as in the community – in the past few months he has delivered RISC-V talks and a BoF at three separate events, and also works regularly to support the RISC-V software ecosystem through participation in RISE as the outreach committee chair. As a representative for Strategic members, he works regularly within the community to gather feedback on current RISC-V board issues to build positive communication and to ensure that Strategic members have a voice on the board.

Krste Asanović is a professor in the EECS Department at the University of California, Berkeley (UC Berkeley). He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005, before returning to join the faculty at UC Berkeley in 2007. His main research areas are computer architecture, VLSI design, parallel programming and operating system design. He is currently director of the UC Berkeley ASPIRE lab tackling the challenge of improving computational efficiency now that transistor scaling is ending. He leads the free RISC-­V ISA project at UC Berkeley, serves as chairman of RISC-V International, and co­founded SiFive Inc. to support commercial use of RISC­-V processors. He received the NSF CAREER award, and is an ACM Distinguished Scientist and an IEEE Fellow.

Lars Bergstrom is a Director of Engineering at Google on the Android team, working on their platform programming languages, including Java, C/C++, and Rust and the supporting tools and libraries. He also serves as Google’s Corporate Director to the Rust Foundation. Before Google, he was at Mozilla Research, initially contributing to the Servo browser project and directing the integration of Rust into Firefox and the partner ecosystem. Later, he led Mozilla’s AR and VR work, shipping software and building OEM relationships on many different devices. He received his Ph.D. in Computer Science from the University of Chicago in 2013.

Marcel Tromp is a Fellow at Infineon Technologies where he drives platform architectures and methodologies as well as processor strategy, including RISC-V adoption.

Marcel started his career at Philips Research as a VLIW CPU architect and later served as chief architect at TriMedia and Equator Technologies. He has held both senior technical and managerial roles defining and delivering complex SoC’s at LSI Logic, Magnum Semiconductor and Cypress Semiconductor.

Marcel holds a MSc. in Electrical Engineering from the University of Twente in the Netherlands.

Mr. Matthew Leung’s main duties lie on the development of next generation processor technologies. His expertise and experience lies in the fields of VLSI design for advanced communication chipsets, microprocessors and artificial intelligence. Mr. Leung received his BSc and MSc degrees of Electrical Engineering in University of Michigan and Stanford University respectively. Before joining Huawei, he worked in Marvell Semiconductor, ASTRI, Sun Microsystems, Apple Computer, etc.

Pei Liu is the Chief Technology Officer of Stream Computing.  With 20+ years of experience in chip development, Pei started at large companies (Intel, Broadcom, Amazon) delivering on industry leading data center products.  Then developed that experience in a strategic direction at startups, including as a founding engineer at Innovium (acquired by Marvell), head of US R&D at Bitmain, co-founding companies, and advising VCs/PEs/startups.  Pei’s commitment to Stream Computing comes from a passion for RISC-V’s open-standard ecosystem of collaboration and democratization of compute; and a phenomenal fit in company vision, technical domain knowledge and cross-cultural expertise.  He has an M.S. and B.S. in Electrical and Computer Engineering from Carnegie Mellon University.

Rabin Sugumar is CEO and Co-Founder of Akeana. Earlier he was a Distinguished Engineer and Chief Architect at Marvell/Cavium in the ThunderX2 Arm server team. ThunderX2 was the first Arm server to achieve single thread and socket level performance comparable to high end Intel Xeon servers and paved the way for Arm servers in the data center. Prior to Cavium he worked on low power threaded and out-of-order SPARC processors at Sun Microsystems and vector supercomputers at Cray Research. Rabin obtained his PhD in Computer Science and Engineering from the University of Michigan.

Ted Speers is a Technical Fellow at Microchip’s FPGA BU, where he is responsible for defining its roadmap for low power, secure, reliable FPGAs and SoC FPGAs. Ted is a RISC-V leader and evangelist and has served on the Board of Directors of RISC-V International since its inception in 2016. He joined Actel (now part of Microchip) in 1987 and held roles in process engineering and product engineering before assuming his current role in 2003. He is co-inventor on 35 U.S. patents. In his role, Ted has consistently defined first of it’s kind products, the most recent example being PolarFireSoC, the first RISC-V based SoC FPGA. Prior to joining Actel, he worked at LSI Logic. Ted has a Bachelor of Science in chemical engineering from Cornell.

Xiaoning Qi is the Vice President of Alibaba Group. Previously, he held senior management and technical positions in companies such as Intel, designing integrated circuits and systems. He sits on the board of directors at several other international organizations including CHIPS Alliance, EEMBC, etc. He has published more than fifty technical papers, a book, and has delivered over three dozen invited talks. He also holds two US patents. Xiaoning received his Ph.D. degree in Electrical Engineering from Stanford University.

Dr. Yankin Tanurhan, Senior Vice President Engineering, Solutions Group at Synopsys is responsible for the Synopsys Processor IP, Security IP, Wireless Interface IP, Smart Subsystems and Non-Volatile Memory businesses. The products in his portfolio include low-power and high-performance ARC embedded CPUs, NPUs, DSPs targeting markets from Mobile, IoT, Embedded Vision, AI/ML, Digital Home, Automotive/Industrial, Security to Storage, ASIP tools with products like ASIP Designer and Programmer, IP Subsystems products like Sensor Fusion, Audio, Vision and Security Subsystems and CMOS-based Non-Volatile OTP and MTP memory IP blocks. His teams additionally develop a wide variety of Security IP from TRNGs to full blown HSMs and IDEs. Lately he extended the R&D activities into Bluetooth and Zigbee products.

Yungang Bao is a Professor of Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) and the director of Research Center of Advanced Computer Systems (ACS) of ICT-CAS. Prof. Bao founded China RISC-V Alliance (CRVA) and serves as the secretary-general of CRVA. His research interests include computer architecture and computer systems. His research work such as Labeled von Neumann Architecture (LvNA), Hybrid Memory Trace Tool (HMTT), Partition-Based DMA Cache and PARSEC 3.0 has been adopted by the industry including Alibaba, Huawei, Intel and the research community. He was a plenary keynote speaker at China National Computer Congress (CNCC) in 2016 and was invited to give a keynote presentation at ARM Research Summit 2018. He was the winner of CCF-Intel Young Faculty Award of the year for 2013. He won CCF-IEEE CS Young Computer Scientist Award and China’s National Lofty Honor for Youth under 40 of the year for 2019.

Dr. Zhangxi Tan is a co-director of the RISC-V International Open-source Laboratory (RIOS), leading open-source IP and software development that helps the RISC-V ecosystem world-class. Dr. Tan is an adjunct professor at Tsinghua-Berkeley Shenzhen Institute (TBSI). He received his PhD in computer science from UC Berkeley in 2013. He is specialized in computer architecture and VLSI designs. After graduating from Berkeley, he joined Pure Storage (NYSE: PSTG) as a Founding Engineer serving as a lead designer for Pure’s award winning FlashBlade product, which generates hundreds of million-dollar revenues every year and have many high-profile customers. Dr. Tan holds more than 20 US patents in flash storage systems and hardware accelerators. He also founded several startup companies in Silicon Valley and China in the chip design industry.