RISC-V International Promotes Andrea Gallo to CEO
RISC-V International announces Andrea Gallo as the organization’s new CEO, effective immediately. Gallo has served as Vice President of Technology at RISC-V International... Read more.
China Initiates Development of RISC-V Talent Training Specifications
Beijing, April 16, 2025 — The RISC-V Talent Training Specification Workshop, organized by the Beijing Institute of Open Source Chip (BOSC) was convened. The workshop... Read more.
RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027
At last month’s Andes Technology RISC-V Con event in San Jose, CA, the company announced a number of partnerships with companies like Imagination Technologies,... Read more.
Quintauris and SEGGER Collaborate on RISC-V Development
May 9, 2025 — SEGGER has announced a partnership with Quintauris to support the growing RISC-V ecosystem through new development tools and hardware for automotive,... Read more.
50 TOPS DC-ROMA RISC-V AI PC is Here!
DeepComputing, in collaboration with Framework and powered by ESWIN Computing’s advanced RISC-V multi-purpose intelligent computing SoC EIC7702X—featuring... Read more.
BrainChip and Andes Unite to Drive Edge AI Breakthroughs on RISC-V Platforms
Laguna Hills, California. BrainChip Holdings Ltd released information it is now integrating Andes Technology’s RISC-V cores with its NPUs. According to the... Read more.
Codasip platform accelerates CHERI adoption
Codasip Prime comprises pre-silicon hardware and software development kits to realise state-of-the-art memory-safe compute. The platform is based on the Codasip... Read more.
Semidynamics Unveils Cervell™: A Scalable RISC-V Neural Processing Unit for Next-Gen AI Workloads
Semidynamics has introduced Cervell™, a highly scalable and fully programmable Neural Processing Unit (NPU) architected on RISC-V. Cervell seamlessly merges CPU,... Read more.
Semidynamics Unveils Cervell™: A Scalable RISC-V Neural Processing Unit for Next-Gen AI Workloads
Semidynamics has introduced Cervell™, a highly scalable and fully programmable Neural Processing Unit (NPU) architected on RISC-V. Cervell seamlessly merges CPU,... Read more.
Andes teams on FPGA prototyping for RISC-V development
Andes Technology has teamed with S2C to develop an FPGA-based prototyping system for its latest RISC-V cores with extensions. The strategic deal uses S2C’s new... Read more.