Project Snapshot Building on the long-standing use of programmable system-on-chips (SoCs) for edge computing in other domains, this work explores their early adoption in application-specific integrated circuit (ASIC) designs for…
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Project Snapshot The Monte Cimone project is a RISC-V-based testbed for High-Performance Computing (HPC) clusters. This work presents Monte Cimone v3 (MCv3), the third iteration of the system, based on…
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Project Snapshot This blog post reports on the experiences and roadmap of the RISER project, which since January 2023 has been developing first-generation all-European RISC-V cloud server and accelerator prototypes…
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Project Snapshot Non-compliant RISC-V extensions remain a practical obstacle for custom and legacy CPU designs. We present a two-phase workflow that uses the RISC-V Unified Database (UDB) as the source…
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Project Snapshot This live demonstration showcases GAPses, an ultra-low-power smart-glasses platform based on an ultra-low power RISC-V multicore processor (GAP9), enabling always-on, real-time, energy-efficient edge processing of electrooculography (EOG) and…
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Project Snapshot Community-maintained Docker packages bring v29 to RISC-V64 within days of official release, not months. Fully automated pipelines compile natively on RISC-V hardware, delivering Docker Engine, CLI, Compose, and…
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Project Snapshot How does performance modeling accelerate real hardware innovation in open RISC-V designs? In this paper, Thales demonstrates a performance model of the CVA6 RISC-V processor, built to evaluate…
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Project Snapshot In this work, we aim to make RVV more accessible to scientific applications by integrating it into the RAJA performance-portability framework. RAJA is a C++ library primarily developed…
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AI verification startup Verifaix explains how its AI Debug Agent automates regression debugging, helping RISC-V developers reduce manual verification effort and accelerate design cycles.
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Project Snapshot Ocelot is an open-source project that enables vector support for the BOOM core. In this generation, we achieve full RVV 1.0 support. The decoupled VPU is connected through…
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