Featured Work Archives

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Oct 16

Optimizing Hardware for Neural Network Inference using Virtual Prototypes

By RISC-V International Staff Featured Work

Project Snapshot Identifying the optimal hardware configuration for running NN inference on edge devices is critical for maximizing performance. Tailoring HW designs to specific applications significantly increases resource utilization. We…

Sep 30

A RISC-V Based Accelerator for Post Quantum Cryptography

By RISC-V International Staff Featured Work

Project Snapshot Post-Quantum Cryptography (PQC) is a topic of increased interest in the past decade, both with regards to the cryptosystem definition and the hardware and software implementations to perform…

Aug 26

CVA6 RISC-V PMP Vulnerabilities against FIA

By RISC-V International Staff Featured Work

Project Snapshot Fault Injection Attacks (FIA) present considerable threats to the security and reliability of embedded systems. FIAs can compromise an embedded processor by altering its clock signal, power supply…

Jul 29

Learning Computer Architecture with a Visual Simulation of RISC-V Processors

By RISC-V International Staff Featured Work

Project Snapshot This work presents an interactive way of teaching computer architecture using Logisim Evolution, enabling students to construct and debug single-cycle and pipelined CPUs. Enhancements to Logisim Evolution allow…

Jun 24

TYRCA: A RISC-V Tightly-Coupled Accelerator For Code-Based Cryptography

By RISC-V International Staff Featured Work

Project Snapshot Post-quantum cryptography (PQC) has garnered significant attention across various communities, particularly with the National Institute of Standards and Technology (NIST) advancing to the fourth round of PQC standardization.…

May 30

HaDes-V – Learning by Puzzling: A Modular Approach to RISC-V Processor Design Education

By RISC-V International Staff Featured Work

Project Snapshot HaDes-V is an Open Educational Resource for learning microcontroller design. It guides through creating a 5-stage pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed and taught…

Mar 24

Simplifying Sail Simulations and Architectural Compatibility Testing

By RISC-V International Staff Featured Work

Greg Sterling from RISC-V International has worked with Carl Perry to create a RISC-V development container to help streamline the process of working with RISC-V related projects. This project aims…

Feb 18

TestRIG – Randomized Testing of RISC-V CPUs

By RISC-V International Staff Featured Work

TestRIG (Testing with Random Instruction Generation) is a testing framework for RISC-V implementations. The RISC-V community has standardized a formal model of the architecture in the Sail language, giving a…

Jan 28

Towards an Integrated Matrix Extension: Workload Analysis of CNN Inference with QEMU TCG Plugings

By RISC-V International Staff Featured Work

Introduction Following the gap analysis done in the second half of 2023, the Vector Special Interest Group (SIG-Vector) has been working on specifying instructions to accelerate matrix operations. Two Task…

Dec 17

Longnail: Hardware Synthesis of CoreDSL Custom Instructions for MCU- and Application-Class Cores

By RISC-V International Staff Featured Work

Tammo Mürmann has just commenced his PhD studies at the Technical University of Darmstadt as part of the Embedded Systems and Applications Group (ESA). During his studies, he already participated…

Featured Work

Optimizing Hardware for Neural Network Inference using Virtual Prototypes

A RISC-V Based Accelerator for Post Quantum Cryptography

CVA6 RISC-V PMP Vulnerabilities against FIA

Learning Computer Architecture with a Visual Simulation of RISC-V Processors

TYRCA: A RISC-V Tightly-Coupled Accelerator For Code-Based Cryptography

HaDes-V – Learning by Puzzling: A Modular Approach to RISC-V Processor Design Education

Simplifying Sail Simulations and Architectural Compatibility Testing

TestRIG – Randomized Testing of RISC-V CPUs

Towards an Integrated Matrix Extension: Workload Analysis of CNN Inference with QEMU TCG Plugings

Longnail: Hardware Synthesis of CoreDSL Custom Instructions for MCU- and Application-Class Cores

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