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First-ever RISC-V Summit Europe Will Demonstrate Technical and Commercial Momentum Across Industries

The Barcelona RISC-V Summit from June 5-9 will focus on industries such as Automotive, High-Performance Compute/Data Center, and Security; Call for Submissions and Sponsorships are now open.


Coming Up

Join us in Santa Clara, CA on November 7-8 for the RISC-V Summit North America 2023 #RISCVSummit #RISCVEverywhere


Upcoming Event

RISC-V Summit Europe 2023

RISC-V Summit Europe brings together developers, architects, technical decision, and policy makers from across the European RISC-V ecosystem. Join us June 5-9 in Barcelona, Spain.




The RISC-V instruction set architecture (ISA) and related specifications are developed, ratified and maintained by RISC-V International contributing members within the RISC-V International Technical Working Groups. Work on the specification is performed on GitHub, and the GitHub issue mechanism can be used to provide input into the specification.



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Calista Redmond, RISC-V International | Open Source Summit NA 2023

Calista Redmond talks with John Furrier & Rob Strechay at Open Source Summit NA 2023 in Vancouver, Canada.


In The News

FOSDEM 2023 schedule – Open-source Embedded, Mobile, IoT, Arm, RISC-V, etc.… projects

After two years of taking place exclusively online, FOSDEM 2023 is back in Brussels, Belgium with thousands expected to attend the 2023 version of the “Free and Open Source Developers’ European Meeting” both onsite and online.


Join RISC-V International

RISC-V International comprises a large member organization building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Through various events and workshops, RISC-V International is changing the way the industry works together and collaborates – creating a new kind of open hardware and software ecosystem. Become a member today and help pioneer the industry’s future de facto ISA for design innovation.

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Safety Critical Real-Time Operating System, SAFERTOS® Available With MiV_RV32 Soft CPU

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SAFERTOS® is a real-time operating system (RTOS) designed specifically for use in safety-critical systems. WITTENSTEIN high integrity systems is a Mi-V Ecosystem Partner of Microchip and have ported SAFERTOS® on…

SOPHGO Donates 50 RISC-V Motherboards – Learn More About the Pioneer Box

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New RISC-V International member SOPHGO is committed to the development and promotion of AI RISC-V CPU and other computing products. RISC-V member Milk-V delivers high-quality RISC-V products to developers, enterprises,…

In the News

Adding RISC-V Vector Cryptography Extension support to QEMU

| In the News | No Comments
RISC-V is an open source instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. Codethink has been working with the RISC-V CPU architecture for several years. We've…

RISE to boost development of open source RISC-V software

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Chip designers are at the heart of a new project to boost the development of open source software for the RISC-V instruction set. The RISC-V Software Ecosystem (RISE) Project is…


Ashling and Imagination announce Ashling’s RiscFree™ C/C++ SDK support for RISC-V-based Catapult family.

| Announcements | No Comments
Embedded World, Mar-14 2023, Nuremberg, Germany. Ashling and Imagination Technologies announced today that Ashling’s RiscFree SDK will provide software development  support for Imagination’s Catapult RISC-V-based IP cores.   RTXM-2200 is the…

First-ever RISC-V Summit Europe Will Demonstrate Technical and Commercial Momentum Across Industries

| Announcements | No Comments
The Barcelona RISC-V Summit from June 5-9 to focus on industries such as Automotive, High Performance Compute/Data Center, and Security; Call for Submissions and Sponsorships now open   BARCELONA, Spain…

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