RISC-V (pronounced “risk-five”) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. The RISC-V ISA was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.



News

  • The RISC-V Memory Consistency Model April 22, 2017 Krste Asanović, Chairman, RISC-V FoundationMemory consistency models (MCMs) are known to flummox even experienced computer architects, so it is perhaps not surprising that recent news articles had some difficulty portraying the nuances behind recent findings by a team of Princeton researchers led by Professor Margaret Martonosi.  The RISC-V Foundation is publishing this article to help the RISC-V community understand the deeper implications of the Princeton study. Executive Summary The Princeton team…

  • RISC-V Enters Mainstream at Embedded World 2017 March 10, 2017 Berkeley, California – Over the last year the RISC-V architecture has evolved from an academic research interest to a mainstream embedded processor technology with a rich ecosystem and a fast-growing number of real-world implementations. As a sign of this progress, a number of companies will be demonstrating commercial implementations of RISC-V products next week at Embedded World 2017, the leading international trade fair for embedded systems (March 14-16, Nuremberg, Germany) https://www.embedded-world.de/enRISC-V…

  • RISC-V chosen as Best Technology of 2016 January 12, 2017 The Linley Group Announces Winners of Annual Analysts’ Choice Awards   In a news release issued today, January 12th, 2017, The Linley Group today announced the winners of its annual Analysts’ Choice Awards which recognize the top semiconductor products of 2016 in seven categories: embedded processors, mobile processors, server processors, processor-IP cores, mobile chip, networking chip, and best technology.  The RISC-V Instruction Set Architecture was selected as the Best Technology of 2016.In…

Workshop Announcements

  • 6th RISC-V Workshop Registration and Call for Papers 6th RISC-V Workshop May 8-11, 2017 Call for Papers and Registration OpenRegistration and the call for presentations / posters is open for the 6th RISC-V Workshop, co-hosted by NVIDIA and the Shanghai Jiao Tong University (SJTU) in Shanghai China on May 8-11, 2017.  As with past workshops, our goals for these events are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe,…

  • 5th RISC-V Workshop Proceedings 5th RISC-V Workshop Proceedings November 29-30, 2016 Proceedings for the 5th RISC-V Workshop, hosted at Google’s Quad campus in Mountain View, California on November 29-30, 2016 are now available with links to the slide presentations and videos shown in the Agenda below.The goals of the workshop are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and build consensus on…

  • 5th RISC-V Workshop Agenda 5th RISC-V Workshop November 29-30, 2016 Registration remains open and the call for presentations / posters is now closed for the 5th RISC-V Workshop, hosted at Google’s Quad campus (468 Ellis Street, Mountain View, CA 94043) on November 29-30, 2016. The Preliminary Agenda is shown below.The goals of the workshop are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and build…

Events

  • IIT Madras RIC2017 April 2017    Under the auspices of the IIT Madras Computer Architecture Initiative and the SHAKTI Processor Project, the team at IIT Madras will host RIC2017 (RISC-V International Conference 2017) this coming April 2nd and 3rd, 2017 in Chennai India.The event Program Committee has plans for a rich technical program covering RISC-V related topics such as : SoC Fabrics IP Blocks Verification Environment Physical Design Flow HW and SW Security support Low Power Systems…

  • Open Source Silicon with RISC-V March 2017 Munich Germany – Join the creators of RISC-V, lowRISC  and the FOSSi Foundation for an afternoon event on Thursday March 23rd, 2017 to learn about their projects, open-source digital hardware and related activities. The RISC-V ISA is free and open, designed by professionals and allows custom extensions. It is now governed by the RISC-V Foundation with many industry members. Among the emerging open implementations, lowRISC aims at creating a fully…

  • RISC-V at EmbeddedWorld March 2017 Be sure to join us at the EmbeddedWorld 2017 Exhibition and Conference in Nuremberg, Germany March 14th-16th, 2017 to learn more about the RISC-V ISA and product offerings form some of our member companies. Antmicro – Hall 4A-121 Antmicro will be showcasing their RISC-V system on module hardware together with the Emul8 simulation framework support for RISC-V which allows for multiple virtual boards booting in one simulation. The AXIOM camera which has…

Workshop Proceedings

  • 5th RISC-V Workshop Proceedings 5th RISC-V Workshop Proceedings November 29-30, 2016 Proceedings for the 5th RISC-V Workshop, hosted at Google’s Quad campus in Mountain View, California on November 29-30, 2016 are now available with links to the slide presentations and videos shown in the Agenda below.The goals of the workshop are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and build consensus on…

  • 4th RISC-V Workshop Proceedings Our 4th RISC-V Workshop was hosted at MIT in Cambridge, MA, this past July 12-13, 2016. The Workshop agenda is shown below together with slides and videos from each of the talks.  We had tremendous participation with 266 registered attendees representing 63 companies and 42 universities from around the world. About the WorkshopThe goals for our RISC-V workshops are for the community to share information about recent activity in various RISC-V projects underway around…

  • 3rd RISC-V Workshop Proceedings Our 3rd RISC-V Workshop was held at the Oracle Conference Center in Redwood Shores, CA January 5-6, 2016. The Workshop agenda is shown below along with the presentation slides and videos from each talk as well as summaries from each of the Breakout Sessions. AboutThe goals of this workshop are for the community to share information about recent activity in the various RISC-V projects underway around the globe, and to build…

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