RISC-V: The Free and Open RISC Instruction Set Architecture

RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

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RISC-V Ecosystem News

August 27, 2018
Reduced Instruction Set Computing Five (RISC-V) is an open Instruction Set Architecture (ISA) designed with small, fast, and low-power real-world implementations in mind....
August 24, 2018
Amelia Dalton discusses data centers, RISC-V and AI cooled data centers on her Fish Fry podcast.What do RISC-V, data center innovation and artificial intelligence have in common?...

RISC-V Foundation Members

Founded in 2015, the RISC-V Foundation comprises more than 100 member organizations building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Through various events and the Foundation's Workshops, the RISC-V Foundation is changing the way the industry works together and collaborates – creating a new kind of open hardware and software ecosystem. Become a member today and help pioneer the industry’s future de facto ISA for design innovation

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