RISC-V International

RISC-V: The Free and Open RISC Instruction Set Architecture

RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

RISC-V Ecosystem News

seL4 is verified on RISC-V!

June 8, 2020

by Gernot Heiser, CSIRO/Data61Sounds great! But what does it mean? seL4seL4 (pronounced ess-e-ell-four) is arguably the world’s most secure operating system (OS) kernel. The OS...

seL4 operating system protects critical systems on RISC-V architecture from cyber-attacks

June 8, 2020

Organisations around the world are developing processors based on the open RISC-V instruction-set architecture (ISA), targeting diverse platforms ranging from embedded and...

The RISC-V opportunity for FPGA | Jim Hogan, Vista Ventures LLC

June 4, 2020

by Jim Hogan, Vista Ventures LLC, Santa Cruz, CA.Sheltering in place has given me time to consider the world around me. I work as an investor in technology and specifically spend...

Strengthening the Internet of Things with a Secure RISC-V IoT Stack

June 3, 2020

By Sandro Pinto, Head of Research and Development at Hex Five Security Inc.The Internet of Things, also known as the IoT, refers to the billions of physical devices around the...

What’s So Important About Processor Extensibility? | Brian Bailey, Semiconductor Engineering

June 2, 2020

What’s So Important About Processor Extensibility?

RISC-V International Members

RISC-V International comprises more than 500 members building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Through various events and workshops, RISC-V International is changing the way the industry works together and collaborates – creating a new kind of open hardware and software ecosystem. Become a member today and help pioneer the industry’s future de facto ISA for design innovation.

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