RISC-V: The Free and Open RISC Instruction Set Architecture

RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

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RISC-V Ecosystem News

June 8, 2020
by Gernot Heiser, CSIRO/Data61Sounds great! But what does it mean? seL4seL4 (pronounced ess-e-ell-four) is arguably the world’s most secure operating system (OS) kernel. The OS...

RISC-V International Members

RISC-V International comprises more than 500 members building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Through various events and workshops, RISC-V International is changing the way the industry works together and collaborates – creating a new kind of open hardware and software ecosystem. Become a member today and help pioneer the industry’s future de facto ISA for design innovation.

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