Join the global edge AI community in Taipei, Nov 11–12, 2025, for keynotes, workshops, demos, and networking with leaders from Intel, Dell, Ceva, Advantech, and more. On Tuesday, November 11th, RISC-V International CEO, Andrea Gallo, will be hosting a workshop that explores the potential of the RISC-V ISA for Edge AI and showcases solutions from our ecosystem organizations, Andes Technology, SiFive, and OpenHW Foundation.
Missed the action? Presentations are available to view on the RISC-V International YouTube Channel!
The RISC-V instruction set architecture (ISA) and related specifications are developed, ratified and maintained by contributing members within the Technical Working Groups. Download the latest releases, and get involved.
RISC-V is revolutionizing the automotive industry by providing a flexible and open architecture that enables customized, efficient computing solutions for advanced driver-assistance systems (ADAS) and autonomous vehicles.
The RISC-V ISA is a common language for the development of AI systems, enabling a software based approach to hardware which unleashes a new level of compute and algorithm innovation, along with a better business case for bringing these new ideas to market.
We’re Showcasing RISC-V at SC25, the World’s Largest Supercomputing ConferenceI’m heading to SC25 in St. Louis next week to advocate for the growing role of RISC-V in high-performance computing (HPC), alongside my peers in the RISC-V HPC special interest group (SIG). High Performance Computing…
EEWorldOnline: MIPS releases multithreaded processor for edge computingEEWorldOnline: MIPS has begun sampling its new I8500 processor, a scalable, multithreaded data movement processor IP designed for real-time, event-driven computing across hyperscale, automotive, industrial, and communications markets. Optimized for edge AI and 5G/6G environments,…
RISC-V International Names Tom Gall as Vice President of TechnologyOpen-technology veteran Gall will drive RISC-V International’s technical vision and collaboration strategy, strengthening the organisation’s push for worldwide adoption of the RISC-V ISA.
The RISC-V instruction set architecture (ISA) offers a highly customizable open standard platform, enabling developers to build, port, and optimize software applications, extensions, and hardware. Its simplicity and modularity enables efficient design and optimization, fostering innovation and reducing development time and cost.
Becoming a member of RISC-V International allows companies to actively influence the development of an open, royalty-free instruction set architecture, driving innovation in custom processor designs. Membership also provides access to a global community of experts and resources, fostering collaboration and accelerating product development.
RISC-V Fundamentals + Foundational Associate Exam Bundle
Designed for computer engineers and programmers to gain skills in RISC-V processors, enhancing your job market competitiveness. Essential learning experience for anyone looking to enhance their career in the tech industry.
