RISC-V Events

RISC-V Sessions at DAC 2016

Be sure to join us at the 53rd Design Automation Conference in Austin Texas the week of June 6th, 2016 for some interesting RISC-V sessions.Professor Krste Asanovic, UC Berkeley and Chairman of the RISC-V Foundation will deliver the Tuesday June 7th SKY Talk at 1pm in the DAC Pavilion entitled: “RISC-V: Instruction Sets Want To Be Free”. The most important interface in a computer system is the instruction set architecture…

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RISC-V Presentation at ESC Boston

  Arun Thomas from BAE Systems was on the agenda at ESC Boston on Wednesday April 13, 2016 presenting an introduction to the RISC-V ISA. His presentation, “Building Open Hardware with RISC-V” is shown below.   

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RISC-V talks at ORCONF-2015

There will be a number of RISC-V-related talks, from both UC Berkeley and external developers, at ORCONF 2015, which will be held between October 9 to October 11 at CERN, Geneva, Switzerland.   Details available on the ORCONF website.

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RISC-V at HotChips

Analyst Kevin Krewell has posted a HotChips preview at EE Times, which mentions the RISC-V Raven-3 presentation to be made in the last session at HotChips by Yunsup Lee.  UC Berkeley will again be sponsoring a table at HotChips to promote RISC-V, so please drop by if you’ll be there and want to chat about RISC-V uptake. 

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Open vs. Proprietary ISAs at CARD 2015

The fourth workshop on Computer Architecture Research Directions (CARD 2015), held in conjunction with the 42nd International Symposium on Computer Architecture, featured a mini-panel titled “Open vs. Proprietary ISAs” with David Patterson making the case for RISC-V.A video of the panel is now available online and can be viewed on YouTube.More about the panel, including the panelists’ position statements, can be found on the CARD 2015 website.

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RISC-V Tutorial at HPCA 2015

February 8, 2015San Francisco Airport Marriott Waterfront Hotel, San Francisco, CA AboutThe RISC-V tutorial will provide an opportunity to learn about the existing RISC-V infrastructure from the RISC-V team. We will first introduce RISC-V, then go through the RISC-V software stack and the Rocket Chip SoC generator. During these talks, we will feature multiple RISC-V silicon implementations as well as FPGA designs and associated software tools. The later bootcamp sessions…

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RISC-V Tutorial at HPCA 2015

We will hold a RISC-V tutorial at HPCA 2015 on Sunday, February 8th.  The tutorial will start at *1:45pm*.The RISC-V tutorial provides an opportunity to learn about the existing RISC-V infrastructure from the RISC-V team. We will first introduce RISC-V, then go through the RISC-V software stack and the Rocket Chip SoC generator. During these talks, we will feature multiple RISC-V silicon implementations as well as FPGA designs and associated software…

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RISC-V at ESSCIRC-2014

We have presented our paper “A 45nm 1.3GHz 16.7 Double-Precision GFLOPS/W RISC-V Processor with Vector Accelerators” at the 40th European Solid-State Circuits Conference, which was held at Venice, Italy. This paper details our 45nm test chip, which has two 64-bit RISC-V Rocket scalar cores, each with a Hwacha vector accelerator attached to it. The paper and the talk will be available online shortly.

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RISC-V at HotChips-26

The RISC-V team was out in force at the HotChips-26 conference manning a sponsor booth.

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The Berkeley RISC-V team pose for a group shot at the end of the conference. From left to right: Steven Bailey, Henry Cook, Sagar Karandikar, Palmer Dabbelt, Krste Asanovic, Adam Izraelevitz, Colin Schmidt, Yunsup Lee, Andrew Waterman, Brian Zimmer, Scott Beamer, David Patterson.

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