RISC-V Events

   Under the auspices of the IIT Madras Computer Architecture Initiative and the SHAKTI Processor Project, the team at IIT Madras will host RIC2017 (RISC-V International Conference 2017) this coming April 2nd and 3rd, 2017 in Chennai India.The event Program Committee has plans for a rich technical program covering RISC-V related topics such as : SoC Fabrics IP Blocks Verification Environment Physical Design Flow HW and SW Security support Low Power Systems…

Munich Germany – Join the creators of RISC-V, lowRISC  and the FOSSi Foundation for an afternoon event on Thursday March 23rd, 2017 to learn about their projects, open-source digital hardware and related activities. The RISC-V ISA is free and open, designed by professionals and allows custom extensions. It is now governed by the RISC-V Foundation with many industry members. Among the emerging open implementations, lowRISC aims at creating a fully…

Be sure to join us at the EmbeddedWorld 2017 Exhibition and Conference in Nuremberg, Germany March 14th-16th, 2017 to learn more about the RISC-V ISA and product offerings form some of our member companies. Antmicro – Hall 4A-121 Antmicro will be showcasing their RISC-V system on module hardware together with the Emul8 simulation framework support for RISC-V which allows for multiple virtual boards booting in one simulation. The AXIOM camera which has…

    In case you missed FOSDEM’17, here’s the full slides of Arun Thomas’ presentation RISC-V Open Hardware for Your Open Source Software.  There’s also a detailed Q&A with Arun describing the content of his talk as well as a video of the full talk.

Be sure to join us at the 53rd Design Automation Conference in Austin Texas the week of June 6th, 2016 for some interesting RISC-V sessions.Professor Krste Asanovic, UC Berkeley and Chairman of the RISC-V Foundation will deliver the Tuesday June 7th SKY Talk at 1pm in the DAC Pavilion entitled: “RISC-V: Instruction Sets Want To Be Free”. The most important interface in a computer system is the instruction set architecture…

  Arun Thomas from BAE Systems was on the agenda at ESC Boston on Wednesday April 13, 2016 presenting an introduction to the RISC-V ISA. His presentation, “Building Open Hardware with RISC-V” is shown below.   

Krste Asanovic will be giving a RISC-V talk at an IoT Silicon Valley Meetup in Mountain View, California on October 27.

There will be a number of RISC-V-related talks, from both UC Berkeley and external developers, at ORCONF 2015, which will be held between October 9 to October 11 at CERN, Geneva, Switzerland.   Details available on the ORCONF website.

Analyst Kevin Krewell has posted a HotChips preview at EE Times, which mentions the RISC-V Raven-3 presentation to be made in the last session at HotChips by Yunsup Lee.  UC Berkeley will again be sponsoring a table at HotChips to promote RISC-V, so please drop by if you’ll be there and want to chat about RISC-V uptake. 

The fourth workshop on Computer Architecture Research Directions (CARD 2015), held in conjunction with the 42nd International Symposium on Computer Architecture, featured a mini-panel titled “Open vs. Proprietary ISAs” with David Patterson making the case for RISC-V.A video of the panel is now available online and can be viewed on YouTube.More about the panel, including the panelists’ position statements, can be found on the CARD 2015 website.