10 Years of RISC-V

David Patterson is likely best-known for the UC Berkeley research projects Reduced Instruction Set Computers (RISC) and Redundant Arrays of Inexpensive Disks (RAID) and for the book Computer Architecture: A Quantitative Approach, written with John Hennessy. He shared the 2017 ACM A.M. Turing Award and the 2022 NAE Charles Draper prize with his co-author. He also served as UC Berkeley’s Computer Science Division chair, the Computing Research Association chair, and president of the Association for Computing Machinery. He is currently a UC Berkeley Professor Emeritus and Distinguished Engineer at Google.

Frans Sijstermans earned his MSc degree in Computer Science from the Eindhoven University of Technology in 1985. He worked as a researcher at Philips in The Netherlands and Palo Alto, USA, until 1998. After that he held various managerial positions at Philips Semiconductors, TriMedia, and Equator. He joined NVIDIA in 2004, where he is responsible for all RISC-V processors, security IP, video codecs, camera & display controllers, vision & DL accelerators, and GSYNC products. He has been active in the open source community as a member of the inaugural board of the RISC-V foundation and the Alliance for Open Media. Also, his team open sourced NVDLA, NVIDIA’s inferencing accelerator.

Grace is a senior at Mills College, pursuing a Bachelor of Arts in Art & Technology and a Bachelor of Arts in Communications. Since 2015 she has been directing, editing, and producing short films, which have featured in six film festivals. Grace has self produced more than ten films, with the “10 Year Anniversary of RISC-V” project being her biggest editing project yet. Check out some of her other work here.

Andreas is the founder at Zero ASIC, a startup on a mission to reduce the barrier to custom silicon. Andreas has spent the better part of his career optimizing processor energy efficiency and design implementation costs. From 2017 to 2020, Andreas served as a program manager at DARPA where he created and managed national research programs in design automation, open source hardware, machine learning, parallel compilers, heterogeneous integration, and analog computing. Andreas received his BA in Physics (’96), BS in EE (’96), and MS in EE in (’97) from the University of Pennsylvania.

Andrew is the William Eckhardt Professor at the  University of Chicago and Editor-in-Chief of the Communications of the ACM. Chien is a global research leader in parallel computing, computer architecture, clusters, and cloud computing. Dr. Chien served as Vice President of Research at Intel Corporation from 2005-2010, leading long-range and “disruptive technologies” research. While at Intel, working with Microsoft and NSF, Chien was instrumental in creation of the Universal Parallel Computing Research Centers (UPCRC) at Berkeley where RISC-V was born. Dr. Chien is an ACM, IEEE, and AAAS Fellow, and has a PhD, MS, and BS from M.I.T.

Andrew serves as SiFive’s Chief Engineer and co-founder. Andrew received his PhD in Computer Science from UC Berkeley, where, weary of the vagaries of existing instruction set architectures, he co-designed the RISC‑V ISA and the first RISC‑V microprocessors with Yunsup Lee. Andrew is one of the main contributors to the open-source RISC‑V based Rocket chip generator and the Chisel project. Andrew also has an MS from UC Berkeley and a BSE from Duke University.

Arvind is Johnson Professor of Computer Science and Head of CS Faculty at MIT. His current research focus is on the rapid development of embedded systems. Arvind received his PhD from the University of Minnesota (1973) and his BTech from IIT Kanpur (1969) and founded Sandburst (1999) and Bluespec (2003). Arvind is an ACM Fellow, an IEEE Fellow, a member of the National Academy of Engineering and the American Academy of Arts and Sciences.

Calista Redmond is the CEO of RISC-V International with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond RISC-V International. Prior to RISC-V International, Calista held a variety of roles at IBM, including Vice President of IBM Z Ecosystem where she led strategic relationships across software vendors, system integrators, business partners, developer communities, and broader engagement across the industry. Focus areas included execution of commercialization strategies, technical and business support for partners, and matchmaker to opportunities across the IBM Z and LinuxOne community. Calista’s background includes building and leading strategic business models within IBM’s Systems Group through open source initiatives including OpenPOWER, OpenDaylight, and Open Mainframe Project. For OpenPOWER, Calista was a leader in drafting the strategy, cultivating the foundation of partners, and nurturing strategic relationships to grow the org from zero to 300+ members. While at IBM, she also drove numerous acquisition and divestiture missions, and several strategic alliances. Prior to IBM, she was an entrepreneur in four successful start-ups in the IT industry. Calista holds degrees from the University of Michigan and Northwestern University.

David is the lead of Fedora/RISCV efforts and Linux Distribution Software Engineer at SiFive. Prior to focusing on RISC-V, David used to work at CERN as Release Manager for CMS Software and later worked on R&D in computing with main focus on alternative architectures (ARMv8 64-bit and PowerPC)

Frankwell Lin is the President and co-founder of Andes Technology, which is a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores. Frankwell received BSEE degree of Electrophysics from the National Chiao-Tung University, Taiwan, and MSEE degree of Electrical and Computer Engineering from Portland State University, Oregon, USA. Before Andes Technology, he was the spokesperson and board member of Farady, a leading fabless ASIC and silicon IP provider. He also led ASIC business development as starting, then on-and-off leading ASIC implementation, chip backend service, IP business development, industry relationship development (IR) in Faraday. Under his management, Andes Technology has been recognized as one of leading suppliers of embedded CPU IP in semiconductor industry. Andes also won the reputation of leading technology company with awards such like 2012 EE Times worldwide Silicon 60 Hot Startups to Watch, 2015 the Deloitte Technology Fast 500 Asia Pacific award, etc. In 2015, President Lin received accolade award of Outstanding Technology Management Performance, Taiwan, for his contribution to the high-tech industry. In parallel to contribution in the industry, he also contributes time and effort in social service for technology evolution. He is Chairman of TEIA (Taiwan Embedded Industry Alliance) from 2010 to 2012. TEIA is a non-profit organization to promote embedded system innovation as well as embedded system value chain engineering talent training, including embedded software, hardware, IP, application, international promotion channel, etc.

Madhu is the CEO and co-founder of InCore Semiconductors, India’s first processor IP company. He is also a coordinator of the IIT Madras Shakti project and a collaborator with the Robert Bosch Centre for Data Sciences and AI. He is a veteran of the electronics and computing technology industry with more than 3 decades of experience in running tech startups and R&D organizations across the world.

Helena is a Security Technologies Fellow at Rambus (Cryptography Research). She directs the foundational security technologies team in charge of research in crypto and post-quantum crypto, side-channel attack countermeasures, secure memories, and Security IP creation overall. She was formerly CTO at Intrinsic-ID and led the Security team at Gemplus before that. She holds a PhD in cryptography and has authored more than 50 peer-reviewed papers and has over 20 issued patents.

Krste Asanović is a professor in the EECS Department at the University of California, Berkeley (UC Berkeley). He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005, before returning to join the faculty at UC Berkeley in 2007. His main research areas are computer architecture, VLSI design, parallel programming and operating system design. He is currently director of the UC Berkeley ASPIRE lab tackling the challenge of improving computational efficiency now that transistor scaling is ending. He leads the free RISC-­V ISA project at UC Berkeley, serves as chairman of RISC-V International, and co­founded SiFive Inc. to support commercial use of RISC­-V processors. He received the NSF CAREER award, and is an ACM Distinguished Scientist and an IEEE Fellow.

Martin is the former EVP and CTO at Western Digital and is now an advisor to the CEO. Fink joined Western Digital in January 2017. Previously, he served as CTO, EVP and Director of Hewlett Packard Labs at HPE Inc and as CTO and EVP of HP, Inc, overseeing HP Labs. In his 30-year career at HP Inc and HPE Inc. Fink worked in a wide range of roles. Fink led the open source and Linux strategy efforts across the company, helping to gain external market leadership. Fink is listed as co-inventor on multiple patents and is the author of The Business and Economics of Linux and Open Source.

Mike is the President and founder of Rumble Development Corporation. Rumble is a small electronic design firm, specializing in the development of low power and high performance cameras. Rumble also licenses image processing and compression IP to many customers. Michael received his undergraduate degree from Harvard University, a Masters degree in Mathematics from the University of Cambridge, and a Ph.D. in Physics from Harvard University.

Richard studied Mathematics and Computer Science at Imperial College, London, at the same time working on the hardware design and testing of X-ray detectors at Daresbury Laboratory in Cheshire, UK. He went on to co-found three start-up companies in the fields of networking, educational software, and search engine optimization. He then joined Red Hat where today he works on virtualization, storage, RISC-V, unikernels, and researching other new technologies.

Rick is President & CEO of the OpenHW Group a not-for-profit, global organization where developers collaborate on open source cores, related IP, tools, and software projects such as the CORE-V Family of open source RISC-V cores. Previously, Rick was Executive Director of the RISC-V Foundation (now RISC-V International) which he founded in 2015 with the support of over 40 Founding Companies driving a new frontier of processor innovation. Rick holds an Executive MBA degree from the University of Ottawa and is an honors graduate of the faculty of Electronics Engineering Technology at Algonquin College.

Nikhil is a co-founder and CTO of Bluespec, Inc.. He received his Ph.D in Computer Science from University of Pennsylvania, was an Associate Professor at MIT, and a researcher at Digital Equipment Corp., working in Programming Languages, Computer Architecture, and Parallel Computing. He’s worked on RISC-V CPU and system designs since 2013, and chaired the RISC-V ISA Formal Specification group 2017-2019. He is a member of ACM, IEEE, and IFIP WG2.8 on Functional Programming.

Stefan is Managing Director at Sutter Hill Ventures (SHV), lead investor in SiFive and also served as the company’s founding CEO. At SHV, Stefan leads investments in computing, networking and security and sits on several boards. Prior to joining SHV in 2012, Stefan served as EVP/GM of The Platform Systems Group at Juniper Networks, overseeing most of its R&D. After joining Juniper’s founding engineering team as an ASIC designer in 1997, his operating career includes several leadership roles at Juniper and Cisco. Stefan holds a BS in Electrical Engineering and Computer Science from Duke University, and a MS in Electrical Engineering from Stanford University.

Tami is a Program Administrator at UC Berkeley with over 20 years experience in the field. She is currently the administrative team lead for the ADEPT Project at Berkeley. Prior to that she was the admin team lead of the ASPIRE and Par Lab projects, and was interim secretary and treasurer of the RISC-V Foundation.

Ted Speers is a Technical Fellow at Microchip’s FPGA BU, where he is responsible for defining its roadmap for low power, secure, reliable FPGAs and SoC FPGAs. Ted is a RISC-V leader and evangelist and has served on the Board of Directors of RISC-V International since its inception in 2016. He joined Actel (now part of Microchip) in 1987 and held roles in process engineering and product engineering before assuming his current role in 2003. He is co-inventor on 35 U.S. patents. In his role, Ted has consistently defined first of it’s kind products, the most recent example being PolarFireSoC, the first RISC-V based SoC FPGA. Prior to joining Actel, he worked at LSI Logic. Ted has a Bachelor of Science in chemical engineering from Cornell.

Yunsup is SiFive’s Chief Technology Officer and co-founder. Yunsup received his PhD from UC Berkeley, where he co-designed the RISC-V ISA and the first RISC-V microprocessors with Andrew Waterman, and led the development of the Hwacha decoupled vector-fetch extension. Yunsup also holds an MS in Computer Science from UC Berkeley and a BS in Computer Science and Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST).

Dr. Zhangxi Tan is a co-director of the RISC-V International Open-source Laboratory (RIOS), leading open-source IP and software development that helps the RISC-V ecosystem world-class. Dr. Tan is an adjunct professor at Tsinghua-Berkeley Shenzhen Institute (TBSI). He received his PhD in computer science from UC Berkeley in 2013. He is specialized in computer architecture and VLSI designs. After graduating from Berkeley, he joined Pure Storage (NYSE: PSTG) as a Founding Engineer serving as a lead designer for Pure’s award winning FlashBlade product, which generates hundreds of million-dollar revenues every year and have many high-profile customers. Dr. Tan holds more than 20 US patents in flash storage systems and hardware accelerators. He also founded several startup companies in Silicon Valley and China in the chip design industry.

Zvonimir Z. Bandić is a research staff member and senior director of Next Generation Platform Technologies at Western Digital Corporation in San Jose, Calif. He received his Bachelor of Science in electrical engineering in 1994 from the University of Belgrade, Yugoslavia, and his Master of Science (1995) and PhD (1999) in applied physics from Caltech, Pasadena, in the field of novel electronic devices based on wide bandgap semiconductors. He is currently focusing on both NAND and emerging Non-Volatile Memories (PCM, ReRAM, MRAM) applications for data center storage and computing, including CPU, memory, networking and storage. He has been awarded over 50 patents in the fields of solid state electronics, solid state disk controller technology, security architecture and storage systems and has published over 50 peer-reviewed papers.