RISC-V is on the rise, as highlighted by the RISC-V Workshop. Multicore, 64-bit versions of RISC-V are available, and there’s support for FPGA and eFPGA versions. I’ve been following the RISC-V movement almost since its inception, and had a chance to try out SiFive’s Arduino-compatible HiFive1 board earlier. It contains a 32-bit, SiFive E310 RISC-V-compatible processor. I say compatible because RISC-V defines an instruction set architecture (ISA), not a processor architecture like one of the Arm Cortex-M architectures. Those define how the architecture is implemented and run an Arm-compatible ISA.
To read more, please visit: http://www.electronicdesign.com/industrial-automation/getting-creative-risc-v