About the Workshop
Registration is now open for the RISC-V Workshop in Barcelona, co-hosted by the Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya (UPC) May 7-10, 2018. The event will be sponsored by NXP and Western Digital.
As with past workshops, this event will bring together the RISC-V community to share RISC-V activities underway around the globe, and build consensus on the future evolution of the instruction set.
Co-Hosted By
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Event Program
- Monday, May 7, 2018 – A half-day of tutorials from the working groups of the RISC-V technical committee. The sessions will cover topics as Base ISA Ratification, BitManip, Compliance, Debug, Formal Spec, Memory Model, Opcode Space Management, Privilege Spec, Security, Software Toolchain and/or Vector Extensions.
- Tuesday, May 8 and Wednesday, May 9, 2018 – Two full days of presentations on RISC-V architecture, commercial and open-source implementations, software and silicon, vectors and security, applications and accelerators, simulation infrastructure and much more. The full program will be released ahead of the event.
- Thursday, May 10, 2018 – The workshop week will conclude with RISC-V Foundation meetings with attendance restricted to members of the RISC-V Foundation. The day will consist of technical and marketing committee meetings to progress the work currently underway within our various Task Groups.
Additional Activities
- Parties, Networking & Demo Zone – No RISC-V workshop is complete without our networking reception with poster sessions and demos. Mix, mingle and share a drink with your peers while learning about the latest RISC-V implementations, and stop by the demo zone to see live demos and explore the latest RISC-V innovations on the market.
- Tour the Barcelona Supercomputing Center – Join your fellow attendees on one of several tours of the BSC during our networking reception. The BSC is located in a former chapel and was featured in Dan Brown’s The Da Vinci Code.