WHO: Andes Technology Corporation, the leading Asia-based supplier of small, low-power, high performance 32/64-bit embedded CPU cores, today announced that it will participate in the TSMC Open Innovation Platform® (OIP) Ecosystem Forum and exhibition.
WHAT: Emerson Hsiao, Senior VP Andes Technology USA Corp. will present “Evaluating the RISC-V Core in TSMC Process Technology – Low Power Perspective” during the breakout sessions of the TSMC OIP Forum. Andes management and technical staff will be on hand throughout the day in the TSMC OIP Exhibition area to explain Andes’ new RISC-V offerings and to answer any questions from attendees.
WHEN: Emerson Hsiao, Senior VP Andes Technology USA Corp. will present on Wednesday, October 3rd at 4:00 PM in the EDA/IP/Services Track of TSMC Open Innovation Platform (OIP) Ecosystem Forum.
WHERE: Visit Andes Technology Corp. in booth 519 of the TSMC OIP Ecosystem Exhibition at the Santa Clara Convention Center, 5001 Great America Parkway, Santa Clara, CA 95054. To schedule a meeting e-mail america@andestech.com.
To read more, please visit: https://globenewswire.com/news-release/2018/09/26/1576707/0/en/Join-Andes-Technology-Corporation-at-the-TSMC-Open-Innovation-Platform-Ecosystem-Forum.html.
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