Keynotes will feature speakers from Antmicro, Facebook, Microchip, NXP, SiFive, Western Digital and more:
Tuesday, Dec. 4, 2018:
- RISC-V State of the Union
- When: 8:50 a.m. – 9:20 a.m. PST
- Who: Krste Asanovic, Co-Founder & Chief Architect, SiFive and Chairman of the Board, RISC-V Foundation
- Unleashing Innovation From Core to Edge
- When: 9:20 a.m. – 9:40 a.m. PST
- Who: Martin Fink, Executive Vice President and Chief Technology Officer of Western Digital
- Enabling the Freedom to Innovate
- When: 9:40 a.m. – 10 a.m. PST
- Who: Patrick Johnson, Vice President, Mixed Signal and FPGA Business Units of Microchip
- The 100X Problem – How to Redefine Silicon for Augmented Reality
- When: 11:20 a.m. – 11:40 a.m. PST
- Who: Robert Shearer, Director of Silicon Architecture and Modeling of Facebook
Wednesday, Dec. 5, 2018:
- A New Golden Age for Computer Architecture: History, Challenges and Opportunities
- When: 8:30 a.m. – 9 a.m. PST
- Who: David Patterson, Vice Chairman, Board of Directors, RISC-V Foundation
- Opportunities and Challenges of Building Silicon in the Cloud
- When: 9 a.m. – 9:20 a.m. PST
- Who: Yunsup Lee, Chief Technology Officer of SiFive and Chairman of the Technical Task Group, RISC-V Foundation
- Deepening the RISC-V Ecosystem to Drive Industry-Wide Adoption
- When: 9:20 a.m. – 9:40 a.m. PST
- Who: Rob Oshana, Vice President, Software Engineering of NXP and Board Member, RISC-V Foundation
- Accelerating Innovation: Why Google’s TPU Was Just the Start
- When: 9:40 a.m. – 10 a.m. PST
- Who: Michael Gielda, Vice President Business Development of Antmicro
The technical tracks, presented by members of the RISC-V community, will focus on Open RISC-V Platforms, RISC-V Accelerators and Security in RISC-V. For more information on each presentation, please see below:
Tuesday, Dec. 4, 2018:
Wednesday, Dec. 5, 2018:
The Summit’s Exhibit Hall will be open Tuesday, Dec. 4 (10 a.m. to 7 p.m. PST) and Wednesday, Dec. 5 (10 a.m. – 3:30 p.m. PST) to showcase RISC-V-based product demonstrations and allow attendees to explore the latest innovations on the market. The Summit will officially open on Monday, Dec. 3 with a Welcome Party (5 – 7 p.m. PST) hosted by Ashling.
Promotional pricing for the three-day Conference and Exhibition Pass has been extended until Monday, Oct. 29. Platinum, Gold and Silver level members of the RISC-V Foundation qualify for discount codes. Please contact info@riscv.org for your member discount code. To learn more about the packages and limited-time promotions, please visit: https://tmt.knect365.com/risc-v-summit/purchase/select-package.
Sponsorship packages, media partnerships and exhibition packages are also available, see details here.
For press interested in attending, please email: risc-v@racepointglobal.com to receive your complimentary pass.
About RISC-V Foundation
RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 100 member organizations building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.