Bit-tech Article: Esperanto Pulls $58m For RISC-V Many-Core Accelerators

First developed back in 2010 at the University of California, Berkeley, RISC-V is a reduced instruction set computing (RISC) instruction set architecture (ISA) designed as competition for everything from Arm in the embedded space to x86 in mainstream and high-performance computing. As well as the benefit of having little legacy cruft yet gathered, the main feature of RISC-V is that it is wholly open: As well as buying chips and intellectual property (IP) off the shelf, users can obtain the design files for the chips and produce them in-house either as direct copies or modified for specific use-cases, all without ever having to pay a single licensing or royalty fee.
It’s a promise that has attracted many: Western Digital has begun transitioning its storage processing products to RISC-V, as has Nvidia for the logic processors in its graphics processing products; Rambus has released RISC-V based security chips; and two enterprise-oriented storage companies have released RISC-V-powered SSDs.
 
To read more, please visit: https://bit-tech.net/news/tech/cpus/esperanto-pulls-58m-for-risc-v-many-core-accelerators/1/.