By Palmer Dabbelt, Engineer at SiFive
We’ve Adopted the CC0-1.0 License
In all honesty, I know very little about the state of open source licensing — since I rarely start a new project I rarely have a choice anyway. As a result, I’ve pretty much just relied on the rest of the RISC-V community to inform me of which license I should use for any given project, and if the license seem sane I go ahead and adopt it. Alex Guo has suggested adopting the CC0-1.0 license for this repository, which seems sane to me so I’ve gone ahead and done so.
RISC-V QEMU Mailing List and Maintainer
The RISC-V QEMU port now has a mailing list, and has picked up Alistair from Western Digital as an additional maintainer. See the pull request for more details.
Zephyr Blog Post
Nate from SiFive has written an excellent blog post detailing the RISC-V Zephyr port, which is in good shape as of the 1.13.0 release.
LLVM Instructions
Bruce from SiFive has written up some instructions for building LLVM, along with how to build binaries for various RISC-V targets. His instructions point to a pre-integration branch containing patches to add support for the full suite of RISC-V ISA extensions.
A Small GCC Code Generation Bug
I was writing up an example and discovered an optimization bug in our GCC port that pretty much explains itself
$ cat test.c
struct valerr {
long value;
long error;
};
struct valerr func(void) {
struct valerr out;
out.value = 0;
out.error = 1;
return out;
}
$ riscv64-sifive-elf-gcc test.c -O3 -S -o-
func:
addi sp,sp,-16
li a0,0
li a1,1
addi sp,sp,16
jr ra
If anyone is interested in poking around our GCC port, this is probably a fun way to get started!
RISC-V Meetup Hosted by Antmicro
I attended this month’s Bay Area RISC-V meetup, which was exciting as usual. There were talks on TensorFlow Light on RISC-V, Renode for RISC-V, security monitors, and open source hardware!
Events
- November 13: RISC-V Microconference at Linux Plumbers Conference in Vancouver, Canada.
- December 3: RISC-V Summit in Santa Clara, CA.