The Register Article: Early To Embed And Early To Rise? Western Digital Drops Veil On SweRVy RISC-V Based Designs

Western Digital today finally flashed the results of its vow to move a billion controller cores to RISC-V designs.
WD said last year it needed an open and extensible CPU architecture for its purpose-built drive controllers and other devices. As we explained then, no one knew for sure what processors WD has used for its disk and SSD controllers. It is known that the firm uses Intel CPUs with its ActiveScale archive systems and Tegile all-flash and hybrid arrays.
Last year, the disk and solid-state drive manufacturer vowed that RISC-V was its future, and today it announced the SweRV core, a networked cache coherency scheme, and a SweRV instruction set simulator.
 
To read more, please visit: https://www.theregister.co.uk/2018/12/04/w_digital_swervs_into_opensource_riscv_controller_cpus/.