Phoronix Article: Western Digital To Open-Source The "SweRV" RISC-V Core In 2019

More than a year ago Western Digital talked up how they would begin designing RISC-V cores and shipping them in devices and that is indeed panning out. The company has unveiled their new SweRV core and plans to open-source it in 2019.
At the RISC-V Summit, Western Digital talked about their continued investment into this royalty-free, open-source processor ISA. Their current RISC-V design is dubbed SweRV and is a 32-bit, 2-way super-scalar design that features a 9-stage pipeline core and clocks up to 1.8GHz and manufactured on a 28nm process. Western Digital plans to use SweRV within flash controllers / storage devices and other embedded designs.
 
To read more, please visit: https://www.phoronix.com/scan.php?page=news_item&px=Western-Digital-SweRV.