Semiconductor Engineering On RISC-V, FOSSi’s Growing Potential

Semiconductor Engineering’s Brian Bailey has published a piece on the growth of RISC-V, including comment from industry experts including SiFive’s Krste Asanovic and Microsemi’s Ted Speers – and the conclusion that 2019 will be a year of major design wins for the open instruction set architecture.
Beginning with a look at the troubles besetting those clinging to Moore’s Law – the observation turned mandated development target by Intel co-founder Gordon Moore that the number of transistors on a leading-edge part trends toward a doubling roughly every 18 months – and the silicon industry’s search for alternatives, Brian’s piece delves into the growth of RISC-V and predictions for the future.
“With RISC-V, any innovation that happens in the hardware, by collaboration, will create an economic benefit that will be massive,” Microsemi’s Ted Speers, one of the industry experts quoted in the piece, explains. “But who gets rewarded, or how the rewards get funnelled, still has to be figured out.”
 
To read more, please visit: https://abopen.com/news/semiconductor-engineering-on-risc-v-fossis-growing-potential/.