PacktPub Article: Western Digital RISC-V SweRV Core Is Now On GitHub

Last week, Western Digital made Verilog sources for its open source RISC-V core publically available on GitHub under Apache 2.0.
‘SweRV Core’ was made by Western Digital for internal use which they decided to contribute to the open source community. The SweRV Core is a 32-bit, nine stage pipeline core which is two-way superscalar. It is small in size and has a simulation performance of up to 4.9 CoreMarks/Mhz. SweRV Core comes supports data-intensive applications like storage controllers, industrial IoT devices, real-time analytics in surveillance systems etc., Running on a 28mm CMOS battery, the power-efficient design has clock speeds up to 1.8Ghz. This core will be seen in future and upcoming WD products.
 
To read more, please visit: https://hub.packtpub.com/western-digital-risc-v-swerv-core-is-now-on-github/.