Western Digital announced three open source innovations including “RISC-V SweRV Core” on Dec. 4, 2018 to promote the development of the ecosystem using RISC-V. They promote the development of specialized computer architecture, such as real time processing and reasoning of big data and fast data.
RISC-V SweRV Core is a bidirectional superscalar processor. Multiple instructions can be executed at the same time, with 32 bit, 9 stage pipeline configuration. The expected performance is 4.9 CoreMarks / Mhz, the maximum clock speed on a 28 mm CMOS processor is 1.8 Ghz. By making it open source this time, users can expect to use IoT (Internet of Things), secure processing, industrial control.
To read more, please visit: https://monoist.atmarkit.co.jp/mn/articles/1902/20/news058.html. Please note that the original article is in Japanese.
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