Andes Technology unveiled its 32-bit A25MP and 64-bit AX25MP RISC-V multicore processors with comprehensive DSP instruction extension. Both support up to four CPU cores and operate at over 1GHz in 28nm process with Linux symmetric multiprocessing (SMP) support. They provide efficient cache coherence among private level-1 caches; include an optional shared level-2 cache; and support I/O coherence for bus masters without caches. To read more, please visit: https://semiengineering.com/week-in-review-design-low-power-34/.]]>