With the global “AI+IoT” application market, the whole industry chain from IC design to terminal integration has also become popular, setting off a wave of “AIoT” technology innovation. Benefiting from this, MCU, which has been based on IoT and has become the “main force” of the market, has now embarked on the road of technical integration of AIOT, starting from a single main “control” and moving toward the goal of “smart interconnection.” The MCU of the AIoT era will no longer be solely responsible for control, and AI capabilities such as reasoning and computing will become standard for MCUs. Under the favorable conditions of China’s AIoT application and the market booming, local MCU manufacturers are expected to seize this opportunity to take advantage of the trend, based on intelligent applications, and gradually close the international manufacturers until they surpass.
Of course, the “AIoT” solution for MCUs is more than just configuring AI-specific accelerators. With the rise of the RISC-V open source architecture, more and more MCU vendors are beginning to recognize the benefits of using RISC-V to improve and reshape their technology. The MCU system architecture is designed to create a general-purpose MCU that combines low-power, high-power, and real-time AI and IoT features, thus avoiding the problems faced by the above-mentioned AI-specific accelerators. Based on the RISC-V instruction set, the MCU can also be extended in architecture. For example, the French startup Greenwaves introduces the concept of multi-core in the intelligent MCU, which can be multi-stream (SIMD). To accelerate the parallel computing in the AI algorithm, the multi-core general-purpose processor is used instead of the dedicated accelerator to accelerate the artificial intelligence algorithm, which achieves high flexibility of algorithm adaptation and can comprehensively cover the requirements of various scenarios of the MCU.
To read more, please visit: http://news.hqew.com/info-345047. Please note that the original article is in Chinese.