Cycle-Accurate Trace Boosts Performance Optimization Capabilities Of UltraSoC Embedded Analytics Infrastructure

UltraSoC today announced new technology within its embedded monitoring and analytics infrastructure that allows designers of high-performance computing, storage and real-time devices to squeeze ultimate levels of performance from their products. The addition of cycle-accurate trace enables developers of real-time applications using UltraSoC’s embedded analytics to see not only what is happening inside devices, but critically, when something occurred.
Cycle-accurate tracing is increasingly important in real-time and performance-critical applications, where engineers need to optimize the operation of their hardware and software code down to the level of single clock cycles – the smallest unit of time recognized by a CPU, GPU, DSP or accelerator. Cycle accurate tracing will initially be available as part of UltraSoC’s processor trace solution for RISC-V, the rapidly-growing open source processor initiative.
The new cycle accurate trace capabilities build on UltraSoC’s leadership in RISC-V development and debug. In early 2018, the company announced the industry’s first and still the only commercial trace encoder IP designed for RISC-V, providing a mechanism to monitor the program execution of a CPU in real time. It encodes instruction execution and, optionally, data memory accesses, and outputs a highly compressed trace format. External software can later take this data and use it to reconstruct the program execution flow. UltraSoC’s RISC-V Trace Encoder is developed to be compliant with RISC-V standards, while offering a number of powerful features such as data and instruction tracing, a range of counters and timers and a fast profiling facility, clearly differentiating it from open source alternatives which implement the baseline RISC-V standard requirements.
 
To read more, please visit: https://www.ultrasoc.com/cycle-accurate-trace-boosts-performance-optimization-capabilities-ultrasoc-embedded-analytics-infrastructure/.