Automated Test Generation Verification IP Elements Focus on Difficult Scenarios for Broad Range of Processor Cores and SoCs.
Breker Verification Systems, the leading provider of advanced test content synthesis solutions, today unveiled the Breker Integrity FASTApps™ Portfolio, a library of automated test generation intellectual property (IP) elements targeting difficult-to-verify processor core and system-on-chip (SoC) scenarios.
The FASTApps provide commercial-grade, high-coverage verification for RISC-V processor cores and the SoC platforms that use them.
“The RISC-V Open ISA concept, while powerful, introduces verification challenges to engineering teams unfamiliar with processor complexities,” observes David Kelf, Breker’s CEO, an active RISC-V Consortium member involved with a public effort to improve RISC-V verification methodologies. “By automating test content generation, Breker’s years of verification experience can be encapsulated and applied across many projects, driving high test coverage with a minimal level of effort.”