Foundation members demo RISC-V-based implementations
WHERE
Hot Chips 29, Flint Center for the Performing Arts, 21250 Stevens Creek Blvd, Cupertino, Calif., 95014
WHEN
Sunday, Aug. 20 to Tuesday, Aug. 22, 2017</>
WHAT
RISC-V® Foundation will exhibit at Hot Chips 29, showcasing the momentum of its Instruction Set Architecture (ISA), the industry’s first open, free architecture. RISC-V founding member, SiFive, will host a session detailing the industry’s first open-source RISC-V system-on-chip (SoC). Representatives from UC San Diego, Cornell and the University of Michigan will speak about Celerity, an open source RISC-V SoC with a neural network accelerator fabric. Speaking sessions include:
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SiFive Freedom SoCs: Industry’s First Open-Source RISC-V Chips
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WHEN
Monday, Aug. 21 from 11:30 a.m. to 12:30 p.m. PT
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WHO
Yunsup Lee at SiFive
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Celerity: An Open Source RISC-V Tiered Accelerator Fabric
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WHEN
Monday, Aug. 21 from 4:15 p.m. to 6:15 p.m. PT
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WHO
Scott Davidson at UC San Diego, Khalid Al-Hawaj at Cornell and Austin Rovinski at the University of Michigan
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Founding member Codasip will be exhibiting its Codix Berkelium (Codix-Bk) family of processors which are fully compliant with the RISC-V open standard.
Founding member Gray Research LLC will present a poster on GRVI Phalanx, a 1,680-core RISC‑V FPGA accelerator which integrates the greatest number of 32-bit RISC processors ever implemented on a chip in any technology. Poster details include:
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GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Framework: A 1680-core, 26 MB SRAM Parallel Processor Overlay on Xilinx UltraScale+ VU9P
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WHEN
Tuesday, Aug. 22
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WHO
Jan Gray at Gray Research
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Additionally, founding member Microsemi will be showcasing information about its Creative Development Board at the RISC-V table. The board enables the quick development of RISC-V projects and will be available for purchase at Future Electronics in September 2017.
To learn more about the RISC-V Foundation, its open architecture and membership information, please visit: https://riscv.org.
About RISC-V Foundation
RISC-V (pronounced “risk-five”) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. The RISC-V ISA was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.
The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.
Media Contacts
Allison DeLeo
Racepoint Global for RISC-V Foundation
Phone: +1 (415) 694-6700
Email: risc-v@racepointglobal.com