RISC-V Members Including Codasip, Dover Microsystems, Imperas, Microsemi and SiFive to Demo New Innovative Products Based on Open, Free RISC-V ISA
WHERE:
Linley Processor Conference 2017, Hyatt Regency Santa Clara, 5101 Great America Pkwy, Santa Clara, Calif., 95054WHEN:
Wednesday, Oct. 4 to Thursday, Oct. 5, 2017WHAT:
The RISC-V Foundation, together with members including Codasip, Dover Microsystems, Imperas, Microsemi and SiFive, will exhibit new RISC-V implementations at the Linley Processor Conference 2017. Named the 2016 “Best New Technology” for the Linley Group Winners of Annual Analysts’ Choice Awards, the RISC-V community of software and hardware companies continues to grow, making the open and free RISC-V ISA the industry’s de facto standard for future design innovation. Additionally, RISC-V Foundation members, UltraSoC and SiFive, will present at this year’s show, speaking sessions include:- Introducing the New RISC-V U54 Coreplex
- When: Wednesday, Oct. 4, 2017 at 1:50 – 3:30 p.m. PT
- Who: Jack Kang at SiFive
- SoCs Need a System-Level Approach: The Case for Embedded Analytics
- When: Tuesday, Oct. 5, 2017 at 8:45 – 10:30 a.m. PT
- Who: Gajinder Panesar at UltraSoC