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Agenda For Inaugural RISC-V Summit in Santa Clara, Calif. from Dec. 3-6

By September 19, 2018October 1st, 2020No Comments

Inaugural RISC-V Summit Agenda

Dec. 3-6, 2018


The RISC-V Foundation announced the agenda for its first annual RISC-V Summit at the Santa Clara Convention Center in Santa Clara, Calif. from Dec. 3-6, 2018. The Summit, in partnership with Informa’s Knowledge & Networking Division, KNect365, will gather the RISC-V ecosystem for a multi-track conference featuring keynotes, tutorials, exhibitions and networking receptions. The RISC-V Summit will host multi-track technical sessions, an exhibition hall and will feature keynotes from Antmicro, Facebook, Microchip, NXP, Qualcomm, SiFive and Western Digital.
The RISC-V Foundation workshops and events around the world celebrate the growth of the ecosystem and showcase major projects and successful technology using the RISC-V ISA. As the RISC-V ecosystem has grown rapidly over the past few years, the RISC-V Foundation’s membership now includes more than 150 organizations, individuals, academics and universities from 25 countries around the world.

This will be a three day event broken down as follows:

  • Monday, Dec. 3, 2018 – Pre-conference day reserved for on-site registration, networking, initial tutorials and the welcome party.
  • Tuesday and Wednesday, Dec. 4-5, 2018 – These two days will follow the traditional two-day format used at previous workshops with presentations covering various RISC-V projects underway within the RISC-V community and will include a poster / demo reception on Tuesday evening.
  • Thursday, Dec. 6, 2018 – The week of the Summit will conclude with RISC-V Foundation member meetings with attendance restricted to members of the RISC-V Foundation.  The day will consist of Technical and Marketing Committee face to face meetings to progress the work currently underway within our various Task Groups.

Monday, Dec. 3, 2018 RISC-V Summit Pre-Conference

Time Event Speaker, Affiliation
9:00am Registration is open from 9:00 a.m. – 6:00 p.m.
10:30am

Tutorial: Running the Zephyr RTOS and Machine Learning with TensorFlow Lite on RISC-V

 Peter Warden, Google and Peter Zierhoffer, Antmicro
12:00pm Lunch
1:30pm Formal Verification of RISC-V processor implementations Edmund Humbenberger and Clifford Wolf, Symbiotic EDA
1:30pm

Running a Linux-Capable Open Source Soft SoC on the Avalanche Board with MicroSemi PolarFire FPGA

 Karol Gugala, Antmicro and Bill Pratt, Future Electronics
3:00pm Networking Break
3:30pm Tutorial: Easy-to-use, FPGA-Accelerated Hardware Simulation of RISC-V Hardware Designs with FireSim on Amazon EC2 F1 Alon Amid, Sagar Karandikar and David Biancolin, UC Berkeley
5:00pm RISC-V Summit Welcome Happy Hour — Sponsored by Ashling

 

Tuesday, Dec. 4, 2018 RISC-V Summit Day 1

 

Time Event Speaker, Affiliation
8:00am Registration is open from 7:30 a.m. – 6:30 p.m.
8:20am Welcome & RISC-V ISA & Foundation Overview Rick O’Connor, RISC-V Foundation
8:40am Keynote: RISC-V State of the Union Krste Asanovic, SiFive and RISC-V Foundation
9:10am Keynote: Unleashing Innovation From Core to Edge Martin Fink, Western Digital
9:40am Keynote: Enabling the Freedom to Innovate Patrick Johnson, Microchip
10:00am Networking Break
10:00am Exhibit Hall Open
10:50am RISC-V Linux Hackathon
11:00am Keynote: The 100X Problem – How to Redefine Silicon for Augmented Reality Robert Shearer, Facebook
11:40am Lunch & Exhibit Hall Visit
11:40am Expo Hall Open
12:00pm Birds of Feather Discussion: Debugging + Tracing Graham Markall, Embecosm
12:25pm RISC-V Linux Hackathon
1:10pm CPU Project in Western Digital: From Embedded Cores for Flash Controllers to Vision of Datacenter Processors with Open Interfaces Zvonimir Bandic, Dejan Vucinic and Robert Golla, Western Digital
1:10pm

Deterministic L2 Cache Solution and Performance in an AMP capable SoC

 Cyril Jean, Microsemi
1:10pm

Embedded Intelligence Everywhere

 Jack Kang, SiFive
1:10pm

Exhibit Hall Open
1:35pm

Sophon Edge AI platform with RISC-V Processor

 Ian Chen, Bitmain
1:35pm NVIDIA’s Deep Learning Accelerator meets SiFive’s Freedom Platform Yunsup Lee, SiFive and Frans Sijstermans, NVIDIA
1:35pm

Formal Methods Need Not Be Black Magic

 Joseph Kiniry and Daniel Zimmerman, Galois
2:00pm Analyzing the Disruptive Impact of Democratized Access to Silicon Technology Andreas Olofsson, DARPA
2:00pm SiFive Freedom Revolution: Customizable RISC-V AI Platform with HBM2 and 56-112Gb/s SerDes Krste Asanovic, SiFive and RISC-V Foundation
2:00pm A FIPS140-2 Compliant Trust Module for Quad 64-bit RISC-V Core Complex Shumpei Kawasaki, SH Consulting KK and Cong-Kha Pham, University of Electro-Communications
2:25pm UVM-based RISC-V Processor Verification Platform Tao Liu and Richard Ho, Google
2:25pm Hwacha: A Data-Parallel RISC-V Extension and Implementation Colin Schmidt and Albert Ou, UC Berkeley
2:25pm Architecture Design Space Exploration Using RISC-V Donato Kava and Sahan Bandara, Boston University
2:25pm RISC-V Linux Hackathon
2:50pm Using the RISC-V PMP with an Embedded RTOS to Achieve Process Separation and Isolation Jean Labrosse, Micrium / Silicon Labs
2:50pm

Embracing a System-Level Approach in the Real World: Combining Arm & RISC-V in a Heterogeneous Designs

 Gajinder Panesar, UltraSoC
2:50pm

Making RISC-V The Most Secure Platform

 Cesare Galarti, Hex Five Security
3:10pm Networking Break
3:40pm

A Processor Description Language Optimized for RISC-V

 Zdenek Prikryl, Codasip
3:40pm

Massively Parallel RISC-V Processing with Transactional Memory

 Steve Zagorianakos, Netronome
3:40pm Panel: RISC-V Security Ecosystem: Open for Business Brandon Lewis, OpenSystems Media; Chaunhua Chang, Andes Technology; Cesare Galarti, Hex Five Security; Anton Sabev, Google and Martin Scott, Rambus
3:40pm Exhibit Hall Open
4:05pm Making a Complex, Linux-enabled SoC Available to Everyone Today with Renode Michael Gielda, Antmicro
4:05pm Accelerating Computational Storage Over NVMe with RISC-V Stephen Bates, Eideticom
4:30pm AI at the Edge Using PULP + eFPGA Timothy Saxe, QuickLogic and Luca Benini, ETH Zurich
4:30pm RISC-V MultiCore Secure Boot Pierre Selwan and Ken Irving, Microsemi, a Microchip company
4:35pm RISC-V Linux Hackathon
4:55pm Extending the RISC-V ISA for Optimized Support of CNNs in a Multi-Core Context Eric Flamand, GreenWaves Technologies
4:55pm Functional Safety and Security, ISO26262, and Their Implications for the RISC-V Ecosystem Gajinder Panesar, UltraSoC and Francesco Rossi, ResilTech
5:30pm Happy Hour on the Expo Floor
7:00pm Innovation Celebration

 

Wednesday, Dec. 5, 2018 RISC-V Summit Day 2

 

Time Event Speaker, Affiliation
8:00am Registration is open from 8:00 a.m. – 5:30 p.m.
8:25am Welcome
8:30am Keynote: A New Golden Age for Computer Architecture: History, Challenges and Opportunities David Patterson, RISC-V Foundation
9:00am Keynote: Opportunities and Challenges of Building Silicon in the Cloud Yunsup Lee, SiFive
9:20am Keynote: Deepening the RISC-V Ecosystem to Drive Industry-Wide Adoption Rob Oshana, NXP
9:40am Keynote: Accelerating Innovation: Why Google’s TPU Was Just the Start Michael Gielda, Antmicro
10:00am Networking Break on the Expo Floor
10:00am Exhibit Hall Open
10:15am RISC-V Linux Hackathon
10:40am Keynote Panel: Opportunities and Challenges in Security for Open Source Hardware Ed Sperling, Semiconductor Engineering; Helena Handschuh, Rambus; Joseph Kiniry, Galois and Richard Newell, Microsemi
11:20am Keynote: RISC-V: Opportunities and challenges in SoCs Greg Wright, Qualcomm Technologies
11:40am Lunch
1:10pm Running Other Architecture Operating Systems and Applications on RISC-V Using QEMU Alistair Francis, Western Digital
1:10pm Domain-Specific Acceleration via AndeStar V5 Processors Charlie Su, Andes Technology Corporation
1:10pm If We Get RISC-V Security Right, It Will Become the Dominate Processor in the $470B IoT Market Jothy Rosenberg, Dover Microsystems
1:10pm Exhibit Hall Open
1:30pm RISC-V Linux Hackathon
1:40pm How to Address RISC-V Compliance in the Era of OPEN ISA and Custom Instructions Lee Moore and Simon Davidmann, Imperas
1:40pm The Esperanto ET-Maxion High Performance Out-of-Order RISC-V Processor Polychronis Xekalakis and Christopher Celio, Esperanto Technologies
1:40pm Never Again: Spectre-Proofing Chip Designs with End-to-End Formal Methods Adam Chlipala, MIT
2:10pm Accelerating Inferencing on the Edge with RISC-V Russell Klein, Mentor, a Siemens Company
2:10pm Methodologies Behind the World’s First RISC-V-based SSD Controller Jihyo Lee, FADU
2:10pm How to Protect RISC-V Against Side-Channel Attacks? Elke De Mulder and Michael Hutter, Rambus
2:40pm Command-Driven Data Transfer Protocols in RISC-V SoCs Gavin Stark, Netronome
2:40pm Machine-Readable Specifications of RISC-V ISA Alexander Kamkin and Andrei Tatarnikov, ISP RAS
2:40pm SiFive TERP: A Trusted Execution Reference Platform for Embedded Secure Applications Palmer Dabbelt and Nathaniel Graff, SiFive
3:00pm Networking Break
3:30pm Introducing New 64GC IP in the SCRx Family of the RISC-V Compatible Cores by Syntacore Alexander Redkin, Syntacore
3:30pm RISC-V Vector Performance Analysis Guy Lemieux, VectorBlox Computing Inc.
3:30pm Keystone: An Open-Source Secure Enclave for RISC-V Processors Dayeol Lee, UC Berkeley
3:55pm Ara: 64-bit RISC-V Vector Implementation in 22nm FDSOI Fabian Schuiki and Matheus Cavalcante, ETH Zurich
3:55pm Design and Implementation of a RISC-V ISA-based In-order Dual Issue Superscalar Processor Libin TT and S. Krishnakumar Rao, C-DAC
3:55pm Establishing a Security Verification Framework For The RISC-V Architecture Jason Oberg, Tortuga Logic
4:30pm Secure Bootstrapping of Trusted Software in RISC-V Ilia Lebedev, MIT

 

Thursday, Dec. 6, 2018 RISC-V Summit Day 3, Member Meetings

 

Time Event
8:00am Registration & Networking
8:30am Board of Directors
8:30am Lunch Room and Members Lounge
9:30am P Extension
9:30am Processor Trace
9:30am Memory Model 2.0
10:30am ISA Formal Specification
10:30am J Extension
10:30am Bitmanip
10:30am Marketing Events
11:30am Vector Extensions
11:30am Marketing Content
11:30am TEE
11:30am Compliance
12:30pm Lunch
1:30pm Cryptographic
1:30pm Marketing Outreach / Research
1:30pm Base Ratification
1:30pm Software
1:30pm Lunch Room and Members Lounge
2:30pm Technical Committee Chair & Vice Chair
2:30pm Marketing Committee
2:30pm SSC & RISC-V SSITH
2:30pm Fast Interupt
3:30pm All Members Closing Session

 
The technical tracks, presented by members of the RISC-V community, will focus on Open RISC-V Platforms, RISC-V Accelerators and Security in RISC-V. For more information on each track, please see below:
Tuesday, Dec. 4, 2018:

Wednesday, Dec. 5, 2018:

 
The Summit’s Exhibit Hall will be open at the following times to showcase RISC-V-based product demonstrations and allow attendees to explore the latest innovations on the market:
Tuesday, Dec. 4, 2018:

  • 10:20 a.m. – 1 p.m. PST
  • 1:10 p.m. – 3:10 p.m. PST

Wednesday, Dec. 5, 2018:

  • 9:55 a.m. – 11:55 a.m. PST
  • 1:25 p.m. – 3 p.m. PST

 
Promotional pricing for the three-day Conference and Exhibition Pass is available until Monday, Oct. 29. Platinum, Gold and Silver level members of the RISC-V Foundation qualify for discount codes. Please contact info@riscv.org for your member discount code. To learn more about the packages and limited-time promotions, please visit: https://tmt.knect365.com/risc-v-summit/purchase/select-package.
Sponsorship packages, media partnerships and exhibition packages are also available, see details here. For press interested in attending, please email: risc-v@racepointglobal.com to receive your complimentary pass.

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