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RISC-V Foundation Announces Agenda For RISC-V Workshop Taiwan Region

By February 12, 2019October 1st, 2020No Comments
WHERE: Ambassador Hotel, No. 188號, Section 2, Zhonghua Rd, East District, Hsinchu City, Taiwan Region 30060
WHEN: Tuesday, March 12 to Wednesday, March 13, 2019
WHAT: The RISC-V Workshop Taiwan Region will showcase the open, expansive and international RISC-V ecosystem, highlighting current and prospective projects and implementations that influence the future evolution of the RISC-V instruction set architecture (ISA), with a focus on the growth of the RISC-V ecosystem across China and Asia.
The event will feature a variety of speaking sessions, along with poster presentations and demonstrations. RISC-V Foundation member companies presenting at the Workshop include: Andes Technology; Codasip; Cryptape Technology; Hex Five Security; MediaTek; Microsemi, a wholly owned subsidiary of Microchip Technology Inc.; Nuclei System Technology; SiFive; Software Hardware Consulting (SH Consulting); Syntacore; and Western Digital. Andes Technology will present the keynote on Tuesday, March 12. The event schedule is as follows:
Tuesday, March 12, 2019:

  • Welcome & Foundation Overview
    • When: 08:30 – 08:45
    • Who: Rick O’Connor, RISC-V Foundation
  • Keynote: Andes Technology
    • When: 08:45 – 09:10
    • Who: Andes Technology
  • Panel: Opportunities & Challenges in AIoT
    • When: 09:15 – 10:00
    • Who: Frankwell Lin, Andes Technology; Steve Lo, Egis Technology Corp; Ted Speers, Microchip Technology; Chen-Yi Lee, National Chiao-Tung University; Zvonimir Bandic, Western Digital
  • RISC-V Technical Committee Update
    • When: 10:30 – 10:45
    • Who: RISC-V Foundation
  • RISC-V Marketing Committee Update
    • When: 10:45 – 11:00
    • Who: Ted Marena, RISC-V Foundation Marketing Committee and Western Digital
  • Status Update of RISC-V P extension task group
    • When: 11:00 – 11:15
    • Who: Chuan-Hua Chang , Andes Technology
  • Simulation Evaluation of Chaining Implementation for the RISC-V Vector Extension
    • When: 11:15 – 11:40
    • Who: Zhen Wei and Wei-Chung Hsu, National Taiwan University
  • RISC-V Segmentation Extension Proposal
    • When: 13:00 – 13:15
    • Who: Wuyang Chung, Freelancer
  • MediaTek RISC-V Processor on Sensorhub Application
    • When: 13:15 – 13:40
    • Who: Jeremy Liu, MediaTek
  • New Members of AndeStar V5 Processor IPs
    • When: 13:45 – 14:10
    • Who: Charlie Su, Andes Technology
  • Our Passion on the Popularization of RISC-V
    • When: 14:15 – 14:40
    • Who: Tony Xu, Nuclei System Technology
  • Platform Security – A Detailed Comparison of RISC-V to Arm’s TrustZone
    • When: 15:10 – 15:35
    • Who: Don Barnetson, Hex Five Security
  • Cryptospec: a Trust Module System for 64-bit RISC-V Core Complex
    • When: 15:40 – 16:05
    • Who: Shumpei Kawasaki, SH Consulting; Cong-Kha Pham, University of Ellectro-Communication
  • Energy-Efficient Face Detection Using Andes RISC-V Processor
    • When: 16:10 – 16:25
    • Who: Chien-Hao Chen and Po Yu Huang, National Chiao Tung University (NCTU)
  • A Different World: a Blockchain-Focused, General-Purpose Applicable Software Sandbox System Based on RISC-V
    • When: 16:25 – 16:50
    • Who: Xuejie Xiao, Cryptape Technology
  • Enabling TVM on RISC-V Architectures with SIMD Instructions
    • When: 16:55 – 17:20
    • Who: Allen Lu, Peakhills Group Corporation; Jenq-Kuen Lee, National Tsing-Hua University
  • Poster Preview Sessions
    • When: 17:25 – 17:40

Wednesday, March 13, 2019:

  • The Updated Status of RISC-V SW
    • When: 09:30 – 09:55
    • Who: Kito Cheng and Greentime Hu, Andes Technology
  • RISC-V Perf Tool Status
    • When: 10:00 – 10:15
    • Who: Alan Kao, Andes Technology
  • Linux on RISC-V – Fedora and Firmware Status Update
    • When: 10:15 – 10:40
    • Who: Wei Fu, Red Hat
  • Toolchain: Compiler Support for Linker Relaxation in RISC-V
    • When: 11:10 – 11:35
    • Who: Shiva Chen and Hsiangkai Wang, Andes Technology
  • Toolchain: Enhanced LLVM Support For RISC-V
    • When: 11:40 – 12:05
    • Who: Chris Jones and Zdenek Prikryl, Codasip
  • Toolchain: RISC-V Configurability in Compliance Test Framework
    • When: 12:10 – 12:35
    • Who: Radek Hajek and Milan Skala, Codasip
  • Datacenter Processors with OmniXtend Interfaces for Shared Memory and AI Workload Acceleration
    • When: 14:05 – 14:30
    • Who: Zvonimir Bandic, Western Digital
  • PolarFire SoC FPGA – AMP Capable Solution for Both Deterministic Real-Time and Rich OS Support
    • When: 14:50 – 15:05
    • Who: Vishakh Rayapeta, Microsemi
  • Enabling Embedded Intelligence
    • When: 15:05 – 15:30
    • Who: Jack Kang, SiFive
  • SCRx Family of the RISC-V Compatible Core IP by Syntacore
    • When: 15:35 – 16:00
    • Who: Alexander Redkin and Pavel Khabarov, Syntacore

To register for the event, please visit: To learn more about sponsorship opportunities, please visit:
For press interested in attending, please email: to receive your complimentary pass. To learn more about the RISC-V Foundation, its open, free architecture and membership information, please visit:
About RISC-V Foundation
RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 200 member organizations building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.


Racepoint Global for RISC-V Foundation
Allison DeLeo
Phone: +1 (415) 694-6700

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