RISC-V International Annual Awards

Yunsup Lee, TSC Chair

CTO, SiFive

Yunsup is SiFive’s Chief Technology Officer and co-founder. Yunsup received his PhD from UC Berkeley, where he co-designed the RISC-V ISA and the first RISC-V microprocessors with Andrew Waterman, and led the development of the Hwacha decoupled vector-fetch extension. Yunsup also holds an MS in Computer Science from UC Berkeley and a BS in Computer Science and Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST).

Krste Asanović

Chief Architect, SiFive

Krste Asanović is a professor in the EECS Department at the University of California, Berkeley (UC Berkeley). He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005, before returning to join the faculty at UC Berkeley in 2007. His main research areas are computer architecture, VLSI design, parallel programming and operating system design. He is currently director of the UC Berkeley ASPIRE lab tackling the challenge of improving computational efficiency now that transistor scaling is ending. He leads the free RISC-­V ISA project at UC Berkeley, serves as chairman of RISC-V International, and co­founded SiFive Inc. to support commercial use of RISC­-V processors. He received the NSF CAREER award, and is an ACM Distinguished Scientist and an IEEE Fellow.

John Hauser

RISC-V, UC Berkeley

Part-time development of floating-point software (mostly Berkeley SoftFloat) and hardware floating-point units (becoming Berkeley HardFloat).

David Patterson

Distinguished Engineer, RIOS Laboratory

David Patterson is likely best-known for the UC Berkeley research projects Reduced Instruction Set Computers (RISC) and Redundant Arrays of Inexpensive Disks (RAID) and for the book Computer Architecture: A Quantitative Approach, written with John Hennessy. He shared the 2017 ACM A.M. Turing Award and the 2022 NAE Charles Draper prize with his co-author. He also served as UC Berkeley’s Computer Science Division chair, the Computing Research Association chair, and president of the Association for Computing Machinery. He is currently a UC Berkeley Professor Emeritus and Distinguished Engineer at Google.

Andrew Waterman

Co-Founder, RISC-V & Co-Founder, SiFive

Andrew serves as SiFive’s Chief Engineer and co-founder. Andrew received his PhD in Computer Science from UC Berkeley, where, weary of the vagaries of existing instruction set architectures, he co-designed the RISC‑V ISA and the first RISC‑V microprocessors with Yunsup Lee. Andrew is one of the main contributors to the open-source RISC‑V based Rocket chip generator and the Chisel project. Andrew also has an MS from UC Berkeley and a BSE from Duke University.

For contributions to RISC-V compiler development, and the RISC-V adjacent benchmarking suite Embench

For dedication and collaboration in many technical groups including co-chair of priv and writer of fasttrack policy

For leadership in the RISC-V trace task group. Formally ratified March 2020

For leadership of RISC-V P-Ext Task Group, progressing RVP spec discussion and development, with draft spec of RVP in v0.8 approaching toward formal.

For leadership of ISA infrastructure and architecture tests groups, engagement and collaboration to ensure contracted deliverables and involvement across work groups