Welcome to the Ultimate Guide to RISC-V Architecture. In this course, our Founder and CEO, Mr. P R Sivakumar, explains the layered architecture of RISC-V open ISA and how we…
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Sipeed has announced a new entry in its Lichee RISC-V family, this time putting its high-performance Lichee 4A RISC-V system-on-module into a full-size laptop chassis: the Lichee Book 4A. "Lichee…
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The IAR safety-certified C-STAT tool is now available in the Functional Safety editions of IAR Embedded Workbench for RISC-V, ARM, and Renesas RL78 architectures. The latest IAR Embedded Workbench for…
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Today, RISC-V pioneer DeepComputing announced that their first RISC-V Mainboard, compatible with the Framework Laptop 13, is about to be released. Sporting a RISC-V StarFive JH7110 SoC, this groundbreaking Mainboard was…
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Alexander Conklin, Head of Hardware Engineering, Rain AI The compute intensive demands of AI workloads have given rise to a new era in accelerator design. In this talk we’ll take…
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RISC-V Banana Pi BPI-F3 development board review and specifications, including demonstrations running Bianbu OS from SpaceMIT (who also developed the K1 RISC-V SoC on which this SBC is based). Watch…
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Florian "Flo" Wohlrab, CEO of OpenHW Group, leads a Canadian-based nonprofit that operates globally, focusing on open-source hardware. The organization specializes in creating industrial-grade, fully open-source RISC-V cores that are…
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Hoehenkirchen, Germany - June 13, 2024 - Under the headline "RISC-V Debugging made Easy", Lauterbach, the leading supplier of RISC-V debug and trace tools, will demonstrate at the RISC-V Summit…
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DeepComputing partners with Canonical to unveil a huge boost to the DC-ROMA RISC-V Laptop family The DC-ROMA RISC-V Laptop II is the world’s first RISC-V laptop pre-installed and powered by…
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LONDON, June 13, 2024 (GLOBE NEWSWIRE) -- Axiomise, a company noted for enabling formal verification adoption, is headed to the RISC-V Summit Europe to demonstrate formalISA, its automated formal RISC-V…
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