Ambassadors and Advocates

Akira Tsukamoto works at National Institute of Advanced Industrial Science and Technology (AIST). His main focusing area is software engineering on network, operating system and system security who enthusiastic on any kind of technical development and have worked on products based on Cell/B.E. and ARM. Received M.S in Computer Science from Columbia University in the City of New York.

Alexander is responsible for the Mixed-Signal ASIC design group at Fraunhofer IMS, a microelectronics research institute located in Duisburg/Germany, which is part of the Fraunhofer society. Alexander had been searching for a license-free computing core suitable for both research work and commercial ASIC development and started the development of RISC-V based systems at Fraunhofer IMS in 2017.

Bruno Levy is a researcher with Inria, the french institute for research in digital science and technology. He is the director of the Nancy Grand-Est research center. As a researcher, he works on computational physics, with applications in fluid simulation and cosmology. As a RISC-V enthousiast and hobbyist, he is the main author and maintainer of femtorv, a minimalist and easy-to-understand RISC-V design tailored for education.

• Website: https://members.loria.fr/BLevy/ and https://orcid.org/0000-0002-7007-3219

I’ve been contributing with the port and test of the Golang language for about an year until it’s release on version 1.14 scheduled for feb/2020. I’ve also ported many projects and contributed with 30+ pull requests for cloud-native applications like Docker, Kubernetes,
Prometheus, Etcd and many more. The ported projects are tracked on https://github.com/carlosedp/riscv-bringup with instructions on how to build from source for many of them. Participating actively in the community on Linux tests for the Kernel ecosystem (Kernel, OpenSBI, U-Boot) and creating guides on how to have Linux on SiFive Unleashed board (https://github.com/carlosedp/riscv-bringup/tree/master/unleashed) and Qemu emulator (https://github.com/carlosedp/riscv-bringup/tree/master/Qemu). Recently have been testing and working together with the community the Linux support on Kendryte K210, another Linux capable board.

Christian is a principal RISC-V architect at NXP. He is working on all aspects of RISC-V including HW design & verification, ISA definition, tools, and software. He is deeply involved with the European RISC-V community and is a driving force behind and within the European cooperation projects like TRISTAN and ISOLDE. In the OpenHW Group, he is leading the Core-V Extension Interface (CV-X-IF)  project. Christian has a PhD and M.Sc. from the Technical University of Munich, both in Electrical Engineering.

Daniel Mangum is the Cloud Lead at Golioth, an IoT platform that enables connecting any hardware in any location to the internet. He previously served in a variety of roles in the upstream Kubernetes project, and is active in multiple other open source circles. Daniel has been a member of RISC-V community for multiple years, hosting a meetup in Durham, NC and writing the RISC-V Bytes series on his blog (https://danielmangum.com/categories/risc-v-bytes). He is a frequent speaker at conferences, meetups, and anywhere else an audience will listen to him passionately promote a future of more open hardware and software.

• Website: https://danielmangum.com/

Daniel likes giving talks and workshops. In their free time, Daniel works on different software, especially operating systems and distributions, bringup and application firmware, with a focus on tooling, integration, and documentation. Daniel created Fiedka the firmware editor and started the Platform System Interface project.

• Mastodon: https://mastodon.social/@CyReVolt
• YouTube: https://youtube.com/@CyReVolt
• Twitch: https://twitch.tv/CyReVolt

Dr. Huang is an accomplished entrepreneur and philanthropist with fourty-two years of experience in high-tech start-up, Initial Public Offering (IPO), merger & acquisition (M&A), and executive management of electronic, consumer, and charity business. Dr. Huang is currently representing Micro Magic Inc. for its multi-Billion IP / M&A business. Dr. Huang has MS and BS degree in Electrical & Computer Engineering, Doctorate degree in Acupuncture & Oriental Medicine, and CSS of Administration & Management from Harvard University. Dr. Huang has six USPTO patents granted in hardware / software / free-cancer-drug, with numerous papers published in journals and magazines, and an invited speaker at various Conferences, Newspaper and TV Programs in both USA and abroad.

Fascinated by embedded systems and the Linux kernel. Advocate for Open Source Hardware and Free Software.

Flo is the CEO of the OpenHW Group an international non profit organization dedicated to curate and maintain high quality, industrial grade, open source RISC-V Cores. Flo is fascinated by RISC-V and help to smoothen accessibility to high quality RISC-V IP and help promote the RISC-V ISA worldwide. He is also one of the first RISC-V International Ambassadors. Before leading the OpenHW Group Flo was Head of Sales for Andes Technology an commercial RISC-V provider, where he took care of the markets in Japan, Europe and Middle East.

I also excessively work on Twitter and Linkedin to keep RISC-V news flowing to all interested (mainly English, sometimes german).

• Meetup: https://www.meetup.com/Munich-RISC-V-Meetup-Group/

Florian Zaruba received his BSc degree from TU Wien in 2014 and his MSc degree from ETH Zurich in 2017. In 2021 he completed his PhD degree at the Integrated Systems Laboratory of ETH Zurich under the supervision of Prof. Dr. Luca Benini. His research interests include design of very large scale integration circuits, energy-efficient high performance computer architectures, and processor design. He is currently affiliated with a deep-tech AI start-up in Zurich and is the Director of Engineering HW/SW Task Groups at OpenHW Group.

Jeffrey “Jefro” Osier-Mixon is an open source strategist and community architect with Red Hat, focused on edge & IoT, automotive, and emerging hardware communities. He is best known in RISC-V circles as a program manager for RISC-V for two years. After moving to Red Hat, he has continued to promote RISC-V, particularly with respect to software in his role as a board alternate and Outreach committee chair for the RISE Project, enabling support for the RISC-V software ecosystem. Jefro speaks and facilitates meetups around RISC-V and RISE several times each year.

Ji Qiu is the technical director of the PLCT Lab, Institute of Software, Chinese Academic of Science. The PLCT Lab is an effective strength both at home and abroad in promoting the open-source software ecosystem for the open-sourced RISC-V. She is one of the upstream maintainers for the RISC-V backend of Chromium V8 and Mozilla SpiderMoneky. She had contributed to leading an RVI and Linux Foundation mentorship project “Porting V8 to RV32” and the porting had already been accepted upstream. She has also made a lot of public representations on RISC-V-related topics in English and Chinese during the last 5 years. She believes RISC-V would be one of the top ISAs in the next few years. She would be honorable and responsible to introduce, motivate, and encourage more students, teachers, professors, and engineers to join the RISC-V’s world as an ambassador. Besides, she is the chairman of the HelloLLVM community, which is an active group focusing on LLVM-based compiler research and development. She founded “Nanpanjiang Project” in April 2023 which is dedicated to helping more female engineers achieve their personal career goals in fundamental software areas such as compilers and virtual machines. She graduated from Nankai University in 2007 with a Bachelor of Science degree in Computer Science and Technology. She got her Ph.D. degree in Computer Architecture from the Institute of Computing Technology, Chinese Academic of Science(CAS) in 2013.

Khem, is a seasoned Embedded Linux architect, Khem has been involved in leading many OpenSource software projects over many years, contributing to various projects e.g. GCC, glibc, Linux, LLVM, Rust, Yocto Project. He is maintainer for several projects e.g. RISC-V architecture port layer for yocto project, OpenEmbedded layer, Yocto clang layer, Rust,  Khem is member of Yocto project’s Technical Steering Committee, and Advisory Council. He has also represented on Linaro’s Technical Steering Committee. He has worked on deploying Embedded Linux systems on devices e.g. Network routers, Access points, Set-top boxes, Smart Cameras. His understanding of opensource development processes is key value for creating products based on OpenSource software. Khem is also frequent speaker on OpenSource conferences e.g. Embedded Linux Conference.

• Podcast: The TMPDIR Podcast

• Website: https://vyomasystems.com/

I work as an RTL design engineer at Semidynamics. As an engineer I participate in the development of a new core based on RISC-V ISA. I’m also a Ph.D student at National Research University of Electronic Technology (MIET). Additionally, I assist my colleagues with a teaching of computer architecture course where as a part of lab assignments, students design a RISC-V  based processor using the Verilog HDL. In my free time, I write my technical blog on Twitter and Telegram about  computer architecture and RISC-V ecosystem in Russian. Scientific interests: floating point computing [IEEE-754, Posit], memory hierarchy.

• Website: https://t.me/cpu_design

Nicolas Brunie got his PhD in Computer Science from ENS de Lyon (France) in 2014. His research focus is Computer Arithmetic. He worked at Kalray, a french fabless silicon company, for over 10 years on the MPPA processors participating in the development of Kalray’s proprietary ISA and working in hardware design (FPU, Crypto accelerator, matrix accelerator), software libraries development and system architecture. In 2021, he joined SiFive to design high performance FPUs before switching to out-of-order and in-order vector execution pipeline micro-architecture and design. Joining SiFive has marked his entry into the RISC-V community. He has been involved in the RISC-V community and in particular some ISA specification groups (cryptography TG and FP SIG) and is the author of a blog about RISC-V: https://fprox.substack.com

Olof Kindgren is a senior digital design engineer working for Qamcom Research & Technology. He became actively involved with free and open source silicon through the OpenRISC project in 2011 and has since then worked on many FOSSi projects with a special interest in tools and collaborations. Notable work include the FuseSoc IP core package manager; SERV, the award-winning RISC-V CPU and ipyxact, and SweRVolf, a reference platform for the SweRV CPU family. In 2015, he also co-founded FOSSi Foundation, a vendor-independent organization with the mission to promote and assist Open Source Silicon in academia, the industry and for hobbyists alike.

Ms. Patty Wenhui Tu is sr. director of blockchain plus technology group of Shanghai Wanxiang Blockchain Inc and chair of the Blockchain SIG within RISC-V International Association. Wanxiang blockchain is a leading player in the blockchain industry with the ambition to build a vibrant blockchain ecosystem and promote the development and application of blockchain. Wanxiang blockchain has developed PlatONE, a privacy-computing-focused consortium blockchain platform with Juzix and practical blockchain solutions for industries like supply chain finance, finished vehicle logistics, biological assets, renewable energy, industrial Internet, digital city etc. Patty joined Wanxiang blockchain in 2018. She is the head of blockchain plus technology group and is in charge of initiating innovative projects integrating IoT, 5G, AI technology with blockchain system, together with partners including IC, IoT devices vendors, carriers, application service providers, financial institutions and so on. She has successfully deployed a variety of IoT + blockchain projects including livestock, smart meter assets financing and petrol chemical commodity financing system etc.

Before join Wanxiang, Patty has about 14-year experience in famous semiconductor companies including Spreadtrum/Unisoc, NXP and Conexant. She is familiar with embedded software system and IC architectures of automotive, mobile, multi-media, connectivity chip products. As security expert, she also joined and contributed to DCAS (Downloadable Conditional Access System) GY/T225-2012, the security specification of STB system by State Administration of Radio, Film and Television, China.

Patty graduated from Zhejiang University, major in information engineering, BEng, in 2001 and attained MBA degree in Shanghai Jiaotong University, in 2010.

Expertise: RISC-V, Emulation, FPGA Acceleration

Tiejun Chen is a technical lead from VMware. Prior to VMware he worked at Wind River System and Intel. In recent years he’s been working on various innovations and explorations involving edge computing, ML/AI, RISC-V, WebAssembly, SmartNIC/DPU, open source, etc. Especially, he always would like to build everything into RISC-V to accelerate the adoption of RISC-V everywhere. Last year he was a Strategic Representative of RISC-V International TSC to contribute to the RISC-V community.

Since Dec 2017, I got a chance to make a presentation for “Fedora on RISC-V”. Then I try to follow the latest development status, and make the some presentations in [over a dozen conferences, see “Fu Wei” sheet]. I also try to help some RISC-V companise to understand Fedora/RHEL/CentOS, understand Opensource ecosystem. I have helped to build Fedora on RISC-V desktop Demo, and test UEFI, Fedora image when I prepared my presentation. I am trying my best to help on RISC-V software ecosystem, building connection with/between RISC-V companies and people. Hope someday we can have a software organization for RISC-V to promote the RISC-V ecosystem for IoT/Enterprise/Edge. I always think RISC-V ISA is the most meaningful work for me and my career. it’s my honor to be a RISC-V Ambassador, and go on working on it.

• Meetup: https://www.meetup.com/shanghai-riscv/

Wei Wu is the co-founder and project director of the PLCT Lab. Under his leadership, the PLCT Lab is contributing to RISC-V ecosystem, especially in GNU Toolchain, LLVM, V8, QEMU and AOSP. He is the chairman of the OSDT working group, which is an active community focusing on open source developer tools and projects. He is passionate about pushing the boundary of the RISC-V ecosystem.

Zeeshan Rafique is a final year student of Computer System Engineering at Usman Institute of Technology, Karachi, Pakistan. For the past one and a half years, he has been working on RISC-V at Micro-Electronics Research Laboratory (community member of RISC-V ). At present, he is learning RISC-V deep and along with that, schooling computer architecture course to his junior enthusiasts too. Through teaching, he aims to convey his knowledge to others. Under his guidance, two batches of 10 students each, from computer science and computer engineering designed their cores and IDEs to automate the process of verification (https://github.com/merledu). Besides, he has attended two webinars on RISC-V as a guest speaker and currently, is writing a book for RISC-V beginners. It will help them to get started with basic gates and reach till 5-stage pipelined core along with SDK and FPGA flow. Furthermore, he is working on GDS and SoC designing to model his RV32IMC core. He is willing to complete the design before December to avail of the opportunity of the SkyWater-130nm shuttle program for fabrication. After tape-out, he plans to write a series of articles on RISC-V basics and advances. This all includes in his Final Year Project. In terms of co-curricular activities, he is an active member of societies (IEEE, ACM, DICE) in his university and a lead organizer of Karachi RISC-V Group.

Abdul Wadood is a Hardware Engineer with expertise in Digital Systems and Computer Architecture. For over two years he has worked on the design and functional verification of RISC-V CPUs. He is experienced with Compiler and Kernel development for Energy Efficient Neural Network Processor Architecture. He has been an active member of the sig-arch-test group at RISC-V International and contributed to supporting the RISC-V privilege ISA testing in the standard Compatibility Test (ACT) framework. He is a former mentee at RISC-V International and Google Summer of Code and contributed to RTL design and verification efforts of notable open-source RISC-V cores (SERV, CVA6, and RocketChip). He holds a bachelor’s degree in Electrical Engineering with notable projects that include the ASIC implementation of an embedded RISC-V CPU and the RTL Design and Verification of a Linux-capable RISC-V CPU (UETRV_Pcore).

Fatima Khurshid is currently working as a Senior Verification Engineer. Over the past four years, she has worked on the verification of RISC-V based processors. Fatima holds a degree in BSc. Electrical Engineering from the University of Engineering and Technology, Lahore. She has contributed in developing and reviewing the RISC-V Foundational Associate (RVFA) Certification.

Mehmet Burak Aykenar graduated from Electrical and Electronics Engineering of Middle East Technical University. He started research on digital design and computer architecture in his last year, then completed his masters degree from the Computer Engineering department of TOBB University of Economics and Technology. After some academic work he started working as a digital design engineer focused on FPGA based avionic systems. Currently he is working as a senior digital design engineer and his main work area is MCU/SoC IC design and FPGA based digital design. He gave lectures as a guest lecturer at various universities on digital design and computer architecture. He regularly publishes video lectures and blog writings  about FPGA design, IC design and RISC-V through his YouTube channel and personal website.

Muhammad Bilal Sakhawat is a senior formal verification engineer. He has been verifying RISC-V based processors for more than 4 years. He holds a Bachelor of Science degree in Electrical Engineering from University of Engineering and Technology, Lahore. He has been an active member of the RISC-V Open-Source community since 2021. He made contributions to RISC-V Compliance Framework and RISC-V Sail (golden reference) Model. He also contributed to creating the RISC-V Foundational Associate (RVFA) exam.

Shahzaib Kashif is a Software Engineering Graduate from Karachi Pakistan. He is one of the pioneers who helped in establishing the Semiconductor Ecosystem in Pakistan with the introduction of RISC-V ISA in Undergraduate level via the Platform of Micro Electronics Research Lab (MERL). He is currently a Research Assistant at MERL, training juniors and leading teams of research interns towards a new era of computing and technology. He is part of the team that designed “SoC-Now”, which is a cloud-based System on Chip Generator, designed to help kickstart the chip design start-ups by providing them with a base level system just by a few clicks. He is also part of the team behind “ChipShop” which is a cloud-based GUI for accelerating SoC design, it uses Chipyard on its backend on the cloud. He has represented Pakistan internationally in RISC-V Summit of 2020, where he and his team presented a tutorial on “Reverse Engineering of Rocket-Chip”.

• Website: https://shahzaibkashif.netlify.app/
• Medium: https://medium.com/@shahzaibceo