Microsemi Corporation subsidiary, today extended its Mi-V ecosystem by unveiling the architecture for a new class of SoC FPGAs that combine the industry’s lowest power mid-range PolarFire™ FPGA family with a complete microprocessor subsystem based on the open, royalty-free RISC-V instruction set architecture (ISA). Announced today at the RISC-V Summit in Santa Clara, California, Microchip’s new PolarFire SoC architecture brings real-time deterministic asymmetric multiprocessing (AMP) capability to Linux platforms in a multi-core coherent central processing unit (CPU) cluster. The PolarFire SoC architecture, developed in collaboration with SiFive, features a flexible 2 MB L2 memory subsystem that can be configured as a cache, scratchpad or a direct access memory. This allows designers to implement deterministic real-time embedded applications simultaneously with a rich operating system for a variety of thermal and space constrained applications in collaborative, networked IoT systems. To read more, please visit: https://investor.microsemi.com/2018-12-04-Industrys-First-RISC-V-SoC-FPGA-Architecture-Brings-Real-Time-to-Linux-Giving-Developers-the-Freedom-to-Innovate-in-Low-Power-Secure-and-Reliable-Designs.]]>